Lines Matching +full:smmu +full:- +full:v3

1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
8  * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
40 #define	 IDR0_ST_LVL_2		(0x1 << IDR0_ST_LVL_S) /* 2-level Stream Table*/
52 #define	 IDR0_CD2L		(1 << 19) /* 2-level Context descriptor table*/
53 #define	 IDR0_VMID16		(1 << 18) /* 16-bit VMID supported */
54 #define	 IDR0_VMW		(1 << 17) /* VMID wildcard-matching */
57 #define	 IDR0_SEV		(1 << 14) /* WFE wake-up events */
59 #define	 IDR0_ASID16		(1 << 12) /* 16-bit ASID supported */
60 #define	 IDR0_NS1ATS		(1 << 11) /* Split-stage ATS not supported */
61 #define	 IDR0_ATS		(1 << 10) /* PCIe ATS supported by SMMU */
64 #define	 IDR0_HTTU_S		6 /* H/W transl. table A-flag and Dirty state */
66 #define	 IDR0_HTTU_A		(0x1 << IDR0_HTTU_S) /* Access flag (A-flag) */
67 #define	 IDR0_HTTU_AD		(0x2 << IDR0_HTTU_S) /* A-flag and Dirty State*/
95 #define	 IDR3_RIL		(1 << 10) /* Range-based Invalidations. */
115 #define	 IDR5_OAS_52		(0x6 << IDR5_OAS_S) /* Reserved in SMMU v3.0 */
125 #define	 CR0_SMMUEN		(1 << 0) /* Non-secure SMMU enable */
161 #define	 CR2_E2H		(1 << 0) /* Enable EL2-E2H translation regime */
176 #define	 STRTAB_BASE_RA		(1UL << 62) /* Read-Allocate. */
192 #define	 CMDQ_BASE_RA		(1UL << 62) /* Read-Allocate. */
202 #define	 EVENTQ_BASE_WA		(1UL << 62) /* Write-Allocate. */
209 #define	 PRIQ_BASE_WA		(1UL < 62) /* Write-Allocate. */
298 #define	 SYNC_0_MSH_NS		(0x0 << SYNC_0_MSH_S) /* Non-shareable */
361 #define	STE1_EATS_S1		(0x2 << STE1_EATS_S) /* Split-stage ATS */
464 #define	CD0_AA64		(1UL << 41) /* TTB{0,1} is AArch64-format TT */