Lines Matching +full:64 +full:mb

73 #define	VM_PHYSSEG_MAX		64
97  * When PAGE_SIZE is 4KB, an allocation size of 16MB is supported in order
98  * to optimize the use of the direct map by UMA.  Specifically, a 64-byte
99  * cache line contains at most 8 L2 BLOCK entries, collectively mapping 16MB
100  * of physical memory.  By reducing the number of distinct 16MB "pages" that
102  * both 2MB page TLB misses and cache misses during the page table walk when
103  * a 2MB page TLB miss does occur.
105  * When PAGE_SIZE is 16KB, an allocation size of 32MB is supported.  This
125  * pages when PAGE_SIZE is 16KB.  Level 1 reservations consist of 32 64KB
150  * split into 2 regions at each end of the 64 bit address space, with an
184  * 64 bit address space, mostly just for convenience.
318 #define	ZERO_REGION_SIZE	(64 * 1024)	/* 64KB */