Lines Matching +full:0 +full:xfff
59 /* Extract CPU affinity levels 0-3 */
60 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff)
61 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff)
62 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff)
63 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff)
64 #define CPU_AFF0_MASK 0xffUL
65 #define CPU_AFF1_MASK 0xff00UL
66 #define CPU_AFF2_MASK 0xff0000UL
67 #define CPU_AFF3_MASK 0xff00000000UL
73 #define CPU_IMPL_ARM 0x41
74 #define CPU_IMPL_BROADCOM 0x42
75 #define CPU_IMPL_CAVIUM 0x43
76 #define CPU_IMPL_DEC 0x44
77 #define CPU_IMPL_FUJITSU 0x46
78 #define CPU_IMPL_HISILICON 0x48
79 #define CPU_IMPL_INFINEON 0x49
80 #define CPU_IMPL_FREESCALE 0x4D
81 #define CPU_IMPL_NVIDIA 0x4E
82 #define CPU_IMPL_APM 0x50
83 #define CPU_IMPL_QUALCOMM 0x51
84 #define CPU_IMPL_MARVELL 0x56
85 #define CPU_IMPL_APPLE 0x61
86 #define CPU_IMPL_INTEL 0x69
87 #define CPU_IMPL_AMPERE 0xC0
88 #define CPU_IMPL_MICROSOFT 0x6D
91 #define CPU_PART_FOUNDATION 0xD00
92 #define CPU_PART_CORTEX_A34 0xD02
93 #define CPU_PART_CORTEX_A53 0xD03
94 #define CPU_PART_CORTEX_A35 0xD04
95 #define CPU_PART_CORTEX_A55 0xD05
96 #define CPU_PART_CORTEX_A65 0xD06
97 #define CPU_PART_CORTEX_A57 0xD07
98 #define CPU_PART_CORTEX_A72 0xD08
99 #define CPU_PART_CORTEX_A73 0xD09
100 #define CPU_PART_CORTEX_A75 0xD0A
101 #define CPU_PART_CORTEX_A76 0xD0B
102 #define CPU_PART_NEOVERSE_N1 0xD0C
103 #define CPU_PART_CORTEX_A77 0xD0D
104 #define CPU_PART_CORTEX_A76AE 0xD0E
105 #define CPU_PART_AEM_V8 0xD0F
106 #define CPU_PART_NEOVERSE_V1 0xD40
107 #define CPU_PART_CORTEX_A78 0xD41
108 #define CPU_PART_CORTEX_A78AE 0xD42
109 #define CPU_PART_CORTEX_A65AE 0xD43
110 #define CPU_PART_CORTEX_X1 0xD44
111 #define CPU_PART_CORTEX_A510 0xD46
112 #define CPU_PART_CORTEX_A710 0xD47
113 #define CPU_PART_CORTEX_X2 0xD48
114 #define CPU_PART_NEOVERSE_N2 0xD49
115 #define CPU_PART_NEOVERSE_E1 0xD4A
116 #define CPU_PART_CORTEX_A78C 0xD4B
117 #define CPU_PART_CORTEX_X1C 0xD4C
118 #define CPU_PART_CORTEX_A715 0xD4D
119 #define CPU_PART_CORTEX_X3 0xD4E
120 #define CPU_PART_NEOVERSE_V2 0xD4F
121 #define CPU_PART_CORTEX_A520 0xD80
122 #define CPU_PART_CORTEX_A720 0xD81
123 #define CPU_PART_CORTEX_X4 0xD82
124 #define CPU_PART_NEOVERSE_V3AE 0xD83
125 #define CPU_PART_NEOVERSE_V3 0xD84
126 #define CPU_PART_CORTEX_X925 0xD85
127 #define CPU_PART_CORTEX_A725 0xD87
128 #define CPU_PART_NEOVERSE_N3 0xD8E
131 #define CPU_PART_THUNDERX 0x0A1
132 #define CPU_PART_THUNDERX_81XX 0x0A2
133 #define CPU_PART_THUNDERX_83XX 0x0A3
134 #define CPU_PART_THUNDERX2 0x0AF
136 #define CPU_REV_THUNDERX_1_0 0x00
137 #define CPU_REV_THUNDERX_1_1 0x01
139 #define CPU_REV_THUNDERX2_0 0x00
142 #define CPU_PART_EMAG8180 0x000
145 #define CPU_PART_AMPERE1 0xAC3
146 #define CPU_PART_AMPERE1A 0xAC4
149 #define CPU_PART_AZURE_COBALT_100 0xD49
152 #define CPU_PART_KRYO400_GOLD 0x804
153 #define CPU_PART_KRYO400_SILVER 0x805
156 #define CPU_PART_M1_ICESTORM 0x022
157 #define CPU_PART_M1_FIRESTORM 0x023
158 #define CPU_PART_M1_ICESTORM_PRO 0x024
159 #define CPU_PART_M1_FIRESTORM_PRO 0x025
160 #define CPU_PART_M1_ICESTORM_MAX 0x028
161 #define CPU_PART_M1_FIRESTORM_MAX 0x029
162 #define CPU_PART_M2_BLIZZARD 0x032
163 #define CPU_PART_M2_AVALANCHE 0x033
164 #define CPU_PART_M2_BLIZZARD_PRO 0x034
165 #define CPU_PART_M2_AVALANCHE_PRO 0x035
166 #define CPU_PART_M2_BLIZZARD_MAX 0x038
167 #define CPU_PART_M2_AVALANCHE_MAX 0x039
169 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff)
170 #define CPU_PART(midr) (((midr) >> 4) & 0xfff)
171 #define CPU_VAR(midr) (((midr) >> 20) & 0xf)
172 #define CPU_ARCH(midr) (((midr) >> 16) & 0xf)
173 #define CPU_REV(midr) (((midr) >> 0) & 0xf)
175 #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24)
176 #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4)
177 #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20)
178 #define CPU_ARCH_TO_MIDR(val) (((val) & 0xf) << 16)
179 #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0)
181 #define CPU_IMPL_MASK (0xff << 24)
182 #define CPU_PART_MASK (0xfff << 4)
183 #define CPU_VAR_MASK (0xf << 20)
184 #define CPU_ARCH_MASK (0xf << 16)
185 #define CPU_REV_MASK (0xf << 0)
203 * as 0 to allow the compiler to remove a dead code thus
214 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \
216 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1))
218 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0
291 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \