Lines Matching +full:el3 +full:-

1 /*-
41 /* AFSR0_EL1 - Auxiliary Fault Status Register 0 */
57 /* AFSR1_EL1 - Auxiliary Fault Status Register 1 */
73 /* AMAIR_EL1 - Auxiliary Memory Attribute Indirection Register */
169 /* CCSIDR_EL1 - Cache Size ID Register */
188 /* CLIDR_EL1 - Cache level ID register */
195 /* CNTKCTL_EL1 - Counter-timer Kernel Control Register */
202 /* CNTKCTL_EL12 - Counter-timer Kernel Control Register */
209 /* CNTP_CTL_EL0 - Counter-timer Physical Timer Control register */
219 /* CNTP_CTL_EL02 - Counter-timer Physical Timer Control register */
227 /* CNTP_CVAL_EL0 - Counter-timer Physical Timer CompareValue register */
234 /* CNTP_CVAL_EL02 - Counter-timer Physical Timer CompareValue register */
242 /* CNTP_TVAL_EL0 - Counter-timer Physical Timer TimerValue register */
249 /* CNTPCT_EL0 - Counter-timer Physical Count register */
257 /* CNTPCTSS_EL0 - Counter-timer Self-Synchronized Physical Count register */
265 /* CNTV_CTL_EL0 - Counter-timer Virtual Timer Control register */
272 /* CNTV_CTL_EL02 - Counter-timer Virtual Timer Control register */
279 /* CNTV_CVAL_EL0 - Counter-timer Virtual Timer CompareValue register */
286 /* CNTV_CVAL_EL02 - Counter-timer Virtual Timer CompareValue register */
293 /* CNTVCTSS_EL0 - Counter-timer Self-Synchronized Virtual Count register */
301 /* CONTEXTIDR_EL1 - Context ID register */
344 /* CSSELR_EL1 - Cache size selection register */
348 /* CTR_EL0 - Cache Type Register */
399 /* CurrentEL - Current Exception Level */
416 /* DBGBCR<n>_EL1 - Debug Breakpoint Control Registers */
438 /* DBGBVR<n>_EL1 - Debug Breakpoint Value Registers */
445 /* DBGWCR<n>_EL1 - Debug Watchpoint Control Registers */
471 /* DBGWVR<n>_EL1 - Debug Watchpoint Value Registers */
478 /* DCZID_EL0 - Data Cache Zero ID register */
479 #define DCZID_DZP		(1 << 4) /* DC ZVA prohibited if non-0 */
1956 /* MAIR_EL1 - Memory Attribute Indirection Register */
1993 /* MDSCR_EL1 - Monitor Debug System Control Register */
2006 /* MIDR_EL1 - Main ID Register */
2013 /* MPIDR_EL1 - Multiprocessor Affinity Register */
2180 /* PAR_EL1 - Physical Address Register */
2314 /* PMCR_EL0 - Perfomance Monitoring Counters */
2325 #define	PMCR_DP				(1ul << 5) /* Disable CCNT if non-invasive debug*/
2328 #define	PMCR_FZO			(1ul << 9) /* Freeze-on-overflow */
2347 #define	PMCR_FZS			(1ul << 32) /* Freeze-on-SPE event */
2359 /* PMEVTYPER<n>_EL0 - Performance Monitoring Event Type */
2371 #define	PMEVTYPER_M			(1 << 26) /* Secure EL3 filtering */
2372 #define	PMEVTYPER_NSH			(1 << 27) /* Non-secure hypervisor filtering */
2373 #define	PMEVTYPER_NSU			(1 << 28) /* Non-secure user filtering */
2374 #define	PMEVTYPER_NSK			(1 << 29) /* Non-secure kernel filtering */
2590 /* SCTLR_EL1 - System Control Register */
2726 /* PSR fields that can be set from 32-bit and 64-bit processes */
2738 /* REVIDR_EL1 - Revision ID Register */
2745 /* TCR_EL1 - Translation Control Register */
2860 /* TTBR0_EL1 & TTBR1_EL1 - Translation Table Base Register 0 & 1 */
2915 /* ZCR_EL1 - SVE Control Register */