Lines Matching +full:4 +full:x
39 #define INSN_SIZE 4
373 #define CTR_CWG_WIDTH 4
376 #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
378 #define CTR_ERG_WIDTH 4
381 #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
383 #define CTR_DLINE_WIDTH 4
386 #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
394 #define CTR_ILINE_WIDTH 4
397 #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
443 #define DBGBVR_EL1_op2 4
479 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
509 #define DBGPRCR_EL1_CRm 4
510 #define DBGPRCR_EL1_op2 4
516 #define ELR_EL1_CRn 4
524 #define ELR_EL12_CRn 4
555 #define ISS_WFx_RN(x) (((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT) argument
567 #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) argument
570 #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) argument
573 #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) argument
576 #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) argument
579 #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) argument
582 #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) argument
722 #define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) argument
725 #define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) argument
728 #define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) argument
731 #define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) argument
734 #define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) argument
737 #define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) argument
750 #define ID_AA64AFR0_EL1_op2 4
770 #define ID_AA64DFR0_DebugVer_WIDTH 4
772 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) argument
779 #define ID_AA64DFR0_TraceVer_SHIFT 4
780 #define ID_AA64DFR0_TraceVer_WIDTH 4
782 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) argument
786 #define ID_AA64DFR0_PMUVer_WIDTH 4
788 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) argument
799 #define ID_AA64DFR0_BRPs_WIDTH 4
801 #define ID_AA64DFR0_BRPs_VAL(x) \ argument
802 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
804 #define ID_AA64DFR0_PMSS_WIDTH 4
806 #define ID_AA64DFR0_PMSS_VAL(x) ((x) & ID_AA64DFR0_PMSS_MASK) argument
810 #define ID_AA64DFR0_WRPs_WIDTH 4
812 #define ID_AA64DFR0_WRPs_VAL(x) \ argument
813 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
815 #define ID_AA64DFR0_CTX_CMPs_WIDTH 4
817 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ argument
818 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
820 #define ID_AA64DFR0_PMSVer_WIDTH 4
822 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) argument
830 #define ID_AA64DFR0_DoubleLock_WIDTH 4
832 #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) argument
836 #define ID_AA64DFR0_TraceFilt_WIDTH 4
838 #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) argument
842 #define ID_AA64DFR0_TraceBuffer_WIDTH 4
844 #define ID_AA64DFR0_TraceBuffer_VAL(x) ((x) & ID_AA64DFR0_TraceBuffer_MASK) argument
848 #define ID_AA64DFR0_MTPMU_WIDTH 4
850 #define ID_AA64DFR0_MTPMU_VAL(x) ((x) & ID_AA64DFR0_MTPMU_MASK) argument
855 #define ID_AA64DFR0_BRBE_WIDTH 4
857 #define ID_AA64DFR0_BRBE_VAL(x) ((x) & ID_AA64DFR0_BRBE_MASK) argument
862 #define ID_AA64DFR0_HPMN0_WIDTH 4
864 #define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK) argument
877 #define ID_AA64DFR1_SPMU_WIDTH 4
879 #define ID_AA64DFR1_SPMU_VAL(x) ((x) & ID_AA64DFR1_SPMU_MASK) argument
883 #define ID_AA64DFR1_PMICNTR_WIDTH 4
885 #define ID_AA64DFR1_PMICNTR_VAL(x) ((x) & ID_AA64DFR1_PMICNTR_MASK) argument
889 #define ID_AA64DFR1_DPFZS_WIDTH 4
891 #define ID_AA64DFR1_DPFZS_VAL(x) ((x) & ID_AA64DFR1_DPFZS_MASK) argument
903 #define ID_AA64ISAR0_AES_SHIFT 4
904 #define ID_AA64ISAR0_AES_WIDTH 4
906 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) argument
911 #define ID_AA64ISAR0_SHA1_WIDTH 4
913 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) argument
917 #define ID_AA64ISAR0_SHA2_WIDTH 4
919 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) argument
924 #define ID_AA64ISAR0_CRC32_WIDTH 4
926 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) argument
930 #define ID_AA64ISAR0_Atomic_WIDTH 4
932 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) argument
936 #define ID_AA64ISAR0_TME_WIDTH 4
941 #define ID_AA64ISAR0_RDM_WIDTH 4
943 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) argument
947 #define ID_AA64ISAR0_SHA3_WIDTH 4
949 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) argument
953 #define ID_AA64ISAR0_SM3_WIDTH 4
955 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) argument
959 #define ID_AA64ISAR0_SM4_WIDTH 4
961 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) argument
965 #define ID_AA64ISAR0_DP_WIDTH 4
967 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) argument
971 #define ID_AA64ISAR0_FHM_WIDTH 4
973 #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) argument
977 #define ID_AA64ISAR0_TS_WIDTH 4
979 #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) argument
984 #define ID_AA64ISAR0_TLB_WIDTH 4
986 #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) argument
991 #define ID_AA64ISAR0_RNDR_WIDTH 4
993 #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) argument
1006 #define ID_AA64ISAR1_DPB_WIDTH 4
1008 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) argument
1012 #define ID_AA64ISAR1_APA_SHIFT 4
1013 #define ID_AA64ISAR1_APA_WIDTH 4
1015 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) argument
1023 #define ID_AA64ISAR1_API_WIDTH 4
1025 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) argument
1033 #define ID_AA64ISAR1_JSCVT_WIDTH 4
1035 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) argument
1039 #define ID_AA64ISAR1_FCMA_WIDTH 4
1041 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) argument
1045 #define ID_AA64ISAR1_LRCPC_WIDTH 4
1047 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) argument
1052 #define ID_AA64ISAR1_GPA_WIDTH 4
1054 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) argument
1058 #define ID_AA64ISAR1_GPI_WIDTH 4
1060 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) argument
1064 #define ID_AA64ISAR1_FRINTTS_WIDTH 4
1066 #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) argument
1070 #define ID_AA64ISAR1_SB_WIDTH 4
1072 #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) argument
1076 #define ID_AA64ISAR1_SPECRES_WIDTH 4
1078 #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) argument
1083 #define ID_AA64ISAR1_BF16_WIDTH 4
1085 #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) argument
1090 #define ID_AA64ISAR1_DGH_WIDTH 4
1092 #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) argument
1096 #define ID_AA64ISAR1_I8MM_WIDTH 4
1098 #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) argument
1102 #define ID_AA64ISAR1_XS_WIDTH 4
1104 #define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) argument
1108 #define ID_AA64ISAR1_LS64_WIDTH 4
1110 #define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) argument
1125 #define ID_AA64ISAR2_WFxT_WIDTH 4
1127 #define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) argument
1130 #define ID_AA64ISAR2_RPRES_SHIFT 4
1131 #define ID_AA64ISAR2_RPRES_WIDTH 4
1133 #define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) argument
1137 #define ID_AA64ISAR2_GPA3_WIDTH 4
1139 #define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) argument
1143 #define ID_AA64ISAR2_APA3_WIDTH 4
1145 #define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) argument
1153 #define ID_AA64ISAR2_MOPS_WIDTH 4
1155 #define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) argument
1159 #define ID_AA64ISAR2_BC_WIDTH 4
1161 #define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) argument
1165 #define ID_AA64ISAR2_PAC_frac_WIDTH 4
1167 #define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) argument
1171 #define ID_AA64ISAR2_CLRBHB_WIDTH 4
1173 #define ID_AA64ISAR2_CLRBHB_VAL(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK) argument
1177 #define ID_AA64ISAR2_PRFMSLC_WIDTH 4
1179 #define ID_AA64ISAR2_PRFMSLC_VAL(x) ((x) & ID_AA64ISAR2_PRFMSLC_MASK) argument
1183 #define ID_AA64ISAR2_RPRFM_WIDTH 4
1185 #define ID_AA64ISAR2_RPRFM_VAL(x) ((x) & ID_AA64ISAR2_RPRFM_MASK) argument
1189 #define ID_AA64ISAR2_CSSC_WIDTH 4
1191 #define ID_AA64ISAR2_CSSC_VAL(x) ((x) & ID_AA64ISAR2_CSSC_MASK) argument
1195 #define ID_AA64ISAR2_ATS1A_WIDTH 4
1197 #define ID_AA64ISAR2_ATS1A_VAL(x) ((x) & ID_AA64ISAR2_ATS1A_MASK) argument
1210 #define ID_AA64MMFR0_PARange_WIDTH 4
1212 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) argument
1220 #define ID_AA64MMFR0_ASIDBits_SHIFT 4
1221 #define ID_AA64MMFR0_ASIDBits_WIDTH 4
1223 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) argument
1227 #define ID_AA64MMFR0_BigEnd_WIDTH 4
1229 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) argument
1233 #define ID_AA64MMFR0_SNSMem_WIDTH 4
1235 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) argument
1239 #define ID_AA64MMFR0_BigEndEL0_WIDTH 4
1241 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) argument
1245 #define ID_AA64MMFR0_TGran16_WIDTH 4
1247 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) argument
1252 #define ID_AA64MMFR0_TGran64_WIDTH 4
1254 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) argument
1258 #define ID_AA64MMFR0_TGran4_WIDTH 4
1260 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) argument
1265 #define ID_AA64MMFR0_TGran16_2_WIDTH 4
1267 #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) argument
1273 #define ID_AA64MMFR0_TGran64_2_WIDTH 4
1275 #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) argument
1280 #define ID_AA64MMFR0_TGran4_2_WIDTH 4
1282 #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) argument
1288 #define ID_AA64MMFR0_ExS_WIDTH 4
1290 #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) argument
1294 #define ID_AA64MMFR0_FGT_WIDTH 4
1296 #define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK) argument
1301 #define ID_AA64MMFR0_ECV_WIDTH 4
1303 #define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK) argument
1317 #define ID_AA64MMFR1_HAFDBS_WIDTH 4
1319 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) argument
1323 #define ID_AA64MMFR1_VMIDBits_SHIFT 4
1324 #define ID_AA64MMFR1_VMIDBits_WIDTH 4
1326 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) argument
1330 #define ID_AA64MMFR1_VH_WIDTH 4
1332 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) argument
1336 #define ID_AA64MMFR1_HPDS_WIDTH 4
1338 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) argument
1343 #define ID_AA64MMFR1_LO_WIDTH 4
1345 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) argument
1349 #define ID_AA64MMFR1_PAN_WIDTH 4
1351 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) argument
1357 #define ID_AA64MMFR1_SpecSEI_WIDTH 4
1359 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) argument
1363 #define ID_AA64MMFR1_XNX_WIDTH 4
1365 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) argument
1369 #define ID_AA64MMFR1_TWED_WIDTH 4
1371 #define ID_AA64MMFR1_TWED_VAL(x) ((x) & ID_AA64MMFR1_TWED_MASK) argument
1375 #define ID_AA64MMFR1_ETS_WIDTH 4
1377 #define ID_AA64MMFR1_ETS_VAL(x) ((x) & ID_AA64MMFR1_ETS_MASK) argument
1382 #define ID_AA64MMFR1_HCX_WIDTH 4
1384 #define ID_AA64MMFR1_HCX_VAL(x) ((x) & ID_AA64MMFR1_HCX_MASK) argument
1388 #define ID_AA64MMFR1_AFP_WIDTH 4
1390 #define ID_AA64MMFR1_AFP_VAL(x) ((x) & ID_AA64MMFR1_AFP_MASK) argument
1394 #define ID_AA64MMFR1_nTLBPA_WIDTH 4
1396 #define ID_AA64MMFR1_nTLBPA_VAL(x) ((x) & ID_AA64MMFR1_nTLBPA_MASK) argument
1400 #define ID_AA64MMFR1_TIDCP1_WIDTH 4
1402 #define ID_AA64MMFR1_TIDCP1_VAL(x) ((x) & ID_AA64MMFR1_TIDCP1_MASK) argument
1406 #define ID_AA64MMFR1_CMOVW_WIDTH 4
1408 #define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK) argument
1412 #define ID_AA64MMFR1_ECBHB_WIDTH 4
1414 #define ID_AA64MMFR1_ECBHB_VAL(x) ((x) & ID_AA64MMFR1_ECBHB_MASK) argument
1427 #define ID_AA64MMFR2_CnP_WIDTH 4
1429 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) argument
1432 #define ID_AA64MMFR2_UAO_SHIFT 4
1433 #define ID_AA64MMFR2_UAO_WIDTH 4
1435 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) argument
1439 #define ID_AA64MMFR2_LSM_WIDTH 4
1441 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) argument
1445 #define ID_AA64MMFR2_IESB_WIDTH 4
1447 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) argument
1451 #define ID_AA64MMFR2_VARange_WIDTH 4
1453 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) argument
1457 #define ID_AA64MMFR2_CCIDX_WIDTH 4
1459 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) argument
1463 #define ID_AA64MMFR2_NV_WIDTH 4
1465 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) argument
1470 #define ID_AA64MMFR2_ST_WIDTH 4
1472 #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) argument
1476 #define ID_AA64MMFR2_AT_WIDTH 4
1478 #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) argument
1482 #define ID_AA64MMFR2_IDS_WIDTH 4
1484 #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) argument
1488 #define ID_AA64MMFR2_FWB_WIDTH 4
1490 #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) argument
1494 #define ID_AA64MMFR2_TTL_WIDTH 4
1496 #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) argument
1500 #define ID_AA64MMFR2_BBM_WIDTH 4
1502 #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) argument
1507 #define ID_AA64MMFR2_EVT_WIDTH 4
1509 #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) argument
1514 #define ID_AA64MMFR2_E0PD_WIDTH 4
1516 #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) argument
1529 #define ID_AA64MMFR3_TCRX_WIDTH 4
1531 #define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK) argument
1534 #define ID_AA64MMFR3_SCTLRX_SHIFT 4
1535 #define ID_AA64MMFR3_SCTLRX_WIDTH 4
1537 #define ID_AA64MMFR3_SCTLRX_VAL(x) ((x) & ID_AA64MMFR3_SCTLRX_MASK) argument
1541 #define ID_AA64MMFR3_S1PIE_WIDTH 4
1543 #define ID_AA64MMFR3_S1PIE_VAL(x) ((x) & ID_AA64MMFR3_S1PIE_MASK) argument
1547 #define ID_AA64MMFR3_S2PIE_WIDTH 4
1549 #define ID_AA64MMFR3_S2PIE_VAL(x) ((x) & ID_AA64MMFR3_S2PIE_MASK) argument
1553 #define ID_AA64MMFR3_S1POE_WIDTH 4
1555 #define ID_AA64MMFR3_S1POE_VAL(x) ((x) & ID_AA64MMFR3_S1POE_MASK) argument
1559 #define ID_AA64MMFR3_S2POE_WIDTH 4
1561 #define ID_AA64MMFR3_S2POE_VAL(x) ((x) & ID_AA64MMFR3_S2POE_MASK) argument
1565 #define ID_AA64MMFR3_AIE_WIDTH 4
1567 #define ID_AA64MMFR3_AIE_VAL(x) ((x) & ID_AA64MMFR3_AIE_MASK) argument
1571 #define ID_AA64MMFR3_MEC_WIDTH 4
1573 #define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) argument
1577 #define ID_AA64MMFR3_SNERR_WIDTH 4
1579 #define ID_AA64MMFR3_SNERR_VAL(x) ((x) & ID_AA64MMFR3_SNERR_MASK) argument
1583 #define ID_AA64MMFR3_ANERR_WIDTH 4
1585 #define ID_AA64MMFR3_ANERR_VAL(x) ((x) & ID_AA64MMFR3_ANERR_MASK) argument
1589 #define ID_AA64MMFR3_SDERR_WIDTH 4
1591 #define ID_AA64MMFR3_SDERR_VAL(x) ((x) & ID_AA64MMFR3_SDERR_MASK) argument
1595 #define ID_AA64MMFR3_ADERR_WIDTH 4
1597 #define ID_AA64MMFR3_ADERR_VAL(x) ((x) & ID_AA64MMFR3_ADERR_MASK) argument
1601 #define ID_AA64MMFR3_Spec_FPACC_WIDTH 4
1603 #define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK) argument
1614 #define ID_AA64MMFR4_EL1_op2 4
1622 #define ID_AA64PFR0_EL1_CRm 4
1625 #define ID_AA64PFR0_EL0_WIDTH 4
1627 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) argument
1630 #define ID_AA64PFR0_EL1_SHIFT 4
1631 #define ID_AA64PFR0_EL1_WIDTH 4
1633 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) argument
1637 #define ID_AA64PFR0_EL2_WIDTH 4
1639 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) argument
1644 #define ID_AA64PFR0_EL3_WIDTH 4
1646 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) argument
1651 #define ID_AA64PFR0_FP_WIDTH 4
1653 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) argument
1658 #define ID_AA64PFR0_AdvSIMD_WIDTH 4
1660 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) argument
1666 #define ID_AA64PFR0_GIC_WIDTH 4
1668 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) argument
1673 #define ID_AA64PFR0_RAS_WIDTH 4
1675 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) argument
1681 #define ID_AA64PFR0_SVE_WIDTH 4
1683 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) argument
1687 #define ID_AA64PFR0_SEL2_WIDTH 4
1689 #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) argument
1693 #define ID_AA64PFR0_MPAM_WIDTH 4
1695 #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) argument
1699 #define ID_AA64PFR0_AMU_WIDTH 4
1701 #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) argument
1706 #define ID_AA64PFR0_DIT_WIDTH 4
1708 #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) argument
1712 #define ID_AA64PFR0_RME_WIDTH 4
1714 #define ID_AA64PFR0_RME_VAL(x) ((x) & ID_AA64PFR0_RME_MASK) argument
1718 #define ID_AA64PFR0_CSV2_WIDTH 4
1720 #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) argument
1726 #define ID_AA64PFR0_CSV3_WIDTH 4
1728 #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) argument
1738 #define ID_AA64PFR1_EL1_CRm 4
1741 #define ID_AA64PFR1_BT_WIDTH 4
1743 #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) argument
1746 #define ID_AA64PFR1_SSBS_SHIFT 4
1747 #define ID_AA64PFR1_SSBS_WIDTH 4
1749 #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) argument
1754 #define ID_AA64PFR1_MTE_WIDTH 4
1756 #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) argument
1762 #define ID_AA64PFR1_RAS_frac_WIDTH 4
1764 #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) argument
1768 #define ID_AA64PFR1_MPAM_frac_WIDTH 4
1770 #define ID_AA64PFR1_MPAM_frac_VAL(x) ((x) & ID_AA64PFR1_MPAM_frac_MASK) argument
1774 #define ID_AA64PFR1_SME_WIDTH 4
1776 #define ID_AA64PFR1_SME_VAL(x) ((x) & ID_AA64PFR1_SME_MASK) argument
1781 #define ID_AA64PFR1_RNDR_trap_WIDTH 4
1783 #define ID_AA64PFR1_RNDR_trap_VAL(x) ((x) & ID_AA64PFR1_RNDR_trap_MASK) argument
1787 #define ID_AA64PFR1_CSV2_frac_WIDTH 4
1789 #define ID_AA64PFR1_CSV2_frac_VAL(x) ((x) & ID_AA64PFR1_CSV2_frac_MASK) argument
1794 #define ID_AA64PFR1_NMI_WIDTH 4
1796 #define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK) argument
1800 #define ID_AA64PFR1_MTE_frac_WIDTH 4
1802 #define ID_AA64PFR1_MTE_frac_VAL(x) ((x) & ID_AA64PFR1_MTE_frac_MASK) argument
1806 #define ID_AA64PFR1_THE_WIDTH 4
1808 #define ID_AA64PFR1_THE_VAL(x) ((x) & ID_AA64PFR1_THE_MASK) argument
1812 #define ID_AA64PFR1_MTEX_WIDTH 4
1814 #define ID_AA64PFR1_MTEX_VAL(x) ((x) & ID_AA64PFR1_MTEX_MASK) argument
1818 #define ID_AA64PFR1_DF2_WIDTH 4
1820 #define ID_AA64PFR1_DF2_VAL(x) ((x) & ID_AA64PFR1_DF2_MASK) argument
1824 #define ID_AA64PFR1_PFAR_WIDTH 4
1826 #define ID_AA64PFR1_PFAR_VAL(x) ((x) & ID_AA64PFR1_PFAR_MASK) argument
1836 #define ID_AA64PFR2_EL1_CRm 4
1845 #define ID_AA64ZFR0_EL1_CRm 4
1846 #define ID_AA64ZFR0_EL1_op2 4
1848 #define ID_AA64ZFR0_SVEver_WIDTH 4
1850 #define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK) argument
1854 #define ID_AA64ZFR0_AES_SHIFT 4
1855 #define ID_AA64ZFR0_AES_WIDTH 4
1857 #define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK) argument
1862 #define ID_AA64ZFR0_BitPerm_WIDTH 4
1864 #define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK) argument
1868 #define ID_AA64ZFR0_BF16_WIDTH 4
1870 #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK) argument
1875 #define ID_AA64ZFR0_SHA3_WIDTH 4
1877 #define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK) argument
1881 #define ID_AA64ZFR0_SM4_WIDTH 4
1883 #define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK) argument
1887 #define ID_AA64ZFR0_I8MM_WIDTH 4
1889 #define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK) argument
1893 #define ID_AA64ZFR0_F32MM_WIDTH 4
1895 #define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK) argument
1899 #define ID_AA64ZFR0_F64MM_WIDTH 4
1901 #define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK) argument
1913 #define ID_ISAR5_SEVL_WIDTH 4
1915 #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) argument
1918 #define ID_ISAR5_AES_SHIFT 4
1919 #define ID_ISAR5_AES_WIDTH 4
1921 #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) argument
1926 #define ID_ISAR5_SHA1_WIDTH 4
1928 #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) argument
1932 #define ID_ISAR5_SHA2_WIDTH 4
1934 #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) argument
1938 #define ID_ISAR5_CRC32_WIDTH 4
1940 #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) argument
1944 #define ID_ISAR5_RDM_WIDTH 4
1946 #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) argument
1950 #define ID_ISAR5_VCMA_WIDTH 4
1952 #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) argument
2021 #define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) argument
2024 #define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) argument
2027 #define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) argument
2034 #define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) argument
2044 #define MVFR0_SIMDReg_WIDTH 4
2046 #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) argument
2050 #define MVFR0_FPSP_SHIFT 4
2051 #define MVFR0_FPSP_WIDTH 4
2053 #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) argument
2058 #define MVFR0_FPDP_WIDTH 4
2060 #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) argument
2065 #define MVFR0_FPTrap_WIDTH 4
2067 #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) argument
2071 #define MVFR0_FPDivide_WIDTH 4
2073 #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) argument
2077 #define MVFR0_FPSqrt_WIDTH 4
2079 #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) argument
2083 #define MVFR0_FPShVec_WIDTH 4
2085 #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) argument
2089 #define MVFR0_FPRound_WIDTH 4
2091 #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) argument
2103 #define MVFR1_FPFtZ_WIDTH 4
2105 #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) argument
2108 #define MVFR1_FPDNaN_SHIFT 4
2109 #define MVFR1_FPDNaN_WIDTH 4
2111 #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) argument
2115 #define MVFR1_SIMDLS_WIDTH 4
2117 #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) argument
2121 #define MVFR1_SIMDInt_WIDTH 4
2123 #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) argument
2127 #define MVFR1_SIMDSP_WIDTH 4
2129 #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) argument
2133 #define MVFR1_SIMDHP_WIDTH 4
2135 #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) argument
2140 #define MVFR1_FPHP_WIDTH 4
2142 #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) argument
2148 #define MVFR1_SIMDFMAC_WIDTH 4
2150 #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) argument
2159 #define OSDLR_EL1_op2 4
2166 #define OSLAR_EL1_op2 4
2174 #define OSLSR_EL1_op2 4
2183 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) argument
2211 #define PMBIDR_P_SHIFT 4
2265 #define PMBSR_EC_VAL(x) (((x) & PMBSR_EC_MASK) >> PMBSR_EC_SHIFT) argument
2323 #define PMCR_X (1ul << 4) /* Export to ext. monitoring (ETM) */
2425 #define PMSCR_PA_SHIFT 4
2454 #define PMSFCR_EL1_op2 4
2497 #define PMSIDR_LDS_SHIFT 4
2505 #define PMSIDR_Interval_VAL(x) (((x) & PMSIDR_Interval_MASK) >> PMSIDR_Interval_SHIFT) argument
2509 #define PMSIDR_Interval_1024 4
2558 #define PMSWINC_EL0_op2 4
2586 #define RNDRRS_CRm 4
2601 #define SCTLR_SA0 (UL(0x1) << 4)
2680 #define SPSR_EL1_CRn 4
2733 #define SPSR_EL12_CRn 4
2812 #define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT)
2831 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) argument
2848 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) argument
2849 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) argument
2923 #define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) argument