Lines Matching +full:4 +full:x
37 #define INSN_SIZE 4
78 #define UL(x) UINT64_C(x) argument
390 #define CTR_CWG_WIDTH 4
393 #define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT))
395 #define CTR_ERG_WIDTH 4
398 #define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT))
400 #define CTR_DLINE_WIDTH 4
403 #define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT))
411 #define CTR_ILINE_WIDTH 4
414 #define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT))
460 #define DBGBVR_EL1_op2 4
496 #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
530 #define DBGPRCR_EL1_CRm 4
531 #define DBGPRCR_EL1_op2 4
537 #define ELR_EL1_CRn 4
545 #define ELR_EL12_CRn 4
576 #define ISS_WFx_RN(x) (((x) & ISS_WFx_RN_MASK) >> ISS_WFx_RN_SHIFT) argument
588 #define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT) argument
591 #define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT) argument
594 #define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT) argument
597 #define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT) argument
600 #define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT) argument
603 #define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT) argument
742 #define ICC_SGI1R_EL1_TL_VAL(x) ((x) & ICC_SGI1R_EL1_TL_MASK) argument
745 #define ICC_SGI1R_EL1_AFF1_VAL(x) ((x) & ICC_SGI1R_EL1_AFF1_MASK) argument
748 #define ICC_SGI1R_EL1_SGIID_VAL(x) ((x) & ICC_SGI1R_EL1_SGIID_MASK) argument
751 #define ICC_SGI1R_EL1_AFF2_VAL(x) ((x) & ICC_SGI1R_EL1_AFF2_MASK) argument
754 #define ICC_SGI1R_EL1_RS_VAL(x) ((x) & ICC_SGI1R_EL1_RS_MASK) argument
757 #define ICC_SGI1R_EL1_AFF3_VAL(x) ((x) & ICC_SGI1R_EL1_AFF3_MASK) argument
770 #define ID_AA64AFR0_EL1_op2 4
790 #define ID_AA64DFR0_DebugVer_WIDTH 4
792 #define ID_AA64DFR0_DebugVer_VAL(x) ((x) & ID_AA64DFR0_DebugVer_MASK) argument
798 #define ID_AA64DFR0_TraceVer_SHIFT 4
799 #define ID_AA64DFR0_TraceVer_WIDTH 4
801 #define ID_AA64DFR0_TraceVer_VAL(x) ((x) & ID_AA64DFR0_TraceVer_MASK) argument
805 #define ID_AA64DFR0_PMUVer_WIDTH 4
807 #define ID_AA64DFR0_PMUVer_VAL(x) ((x) & ID_AA64DFR0_PMUVer_MASK) argument
817 #define ID_AA64DFR0_BRPs_WIDTH 4
819 #define ID_AA64DFR0_BRPs_VAL(x) \ argument
820 ((((x) >> ID_AA64DFR0_BRPs_SHIFT) & 0xf) + 1)
822 #define ID_AA64DFR0_PMSS_WIDTH 4
824 #define ID_AA64DFR0_PMSS_VAL(x) ((x) & ID_AA64DFR0_PMSS_MASK) argument
828 #define ID_AA64DFR0_WRPs_WIDTH 4
830 #define ID_AA64DFR0_WRPs_VAL(x) \ argument
831 ((((x) >> ID_AA64DFR0_WRPs_SHIFT) & 0xf) + 1)
833 #define ID_AA64DFR0_CTX_CMPs_WIDTH 4
835 #define ID_AA64DFR0_CTX_CMPs_VAL(x) \ argument
836 ((((x) >> ID_AA64DFR0_CTX_CMPs_SHIFT) & 0xf) + 1)
838 #define ID_AA64DFR0_PMSVer_WIDTH 4
840 #define ID_AA64DFR0_PMSVer_VAL(x) ((x) & ID_AA64DFR0_PMSVer_MASK) argument
847 #define ID_AA64DFR0_DoubleLock_WIDTH 4
849 #define ID_AA64DFR0_DoubleLock_VAL(x) ((x) & ID_AA64DFR0_DoubleLock_MASK) argument
853 #define ID_AA64DFR0_TraceFilt_WIDTH 4
855 #define ID_AA64DFR0_TraceFilt_VAL(x) ((x) & ID_AA64DFR0_TraceFilt_MASK) argument
859 #define ID_AA64DFR0_TraceBuffer_WIDTH 4
861 #define ID_AA64DFR0_TraceBuffer_VAL(x) ((x) & ID_AA64DFR0_TraceBuffer_MASK) argument
865 #define ID_AA64DFR0_MTPMU_WIDTH 4
867 #define ID_AA64DFR0_MTPMU_VAL(x) ((x) & ID_AA64DFR0_MTPMU_MASK) argument
872 #define ID_AA64DFR0_BRBE_WIDTH 4
874 #define ID_AA64DFR0_BRBE_VAL(x) ((x) & ID_AA64DFR0_BRBE_MASK) argument
879 #define ID_AA64DFR0_HPMN0_WIDTH 4
881 #define ID_AA64DFR0_HPMN0_VAL(x) ((x) & ID_AA64DFR0_HPMN0_MASK) argument
902 #define ID_AA64ISAR0_AES_SHIFT 4
903 #define ID_AA64ISAR0_AES_WIDTH 4
905 #define ID_AA64ISAR0_AES_VAL(x) ((x) & ID_AA64ISAR0_AES_MASK) argument
910 #define ID_AA64ISAR0_SHA1_WIDTH 4
912 #define ID_AA64ISAR0_SHA1_VAL(x) ((x) & ID_AA64ISAR0_SHA1_MASK) argument
916 #define ID_AA64ISAR0_SHA2_WIDTH 4
918 #define ID_AA64ISAR0_SHA2_VAL(x) ((x) & ID_AA64ISAR0_SHA2_MASK) argument
923 #define ID_AA64ISAR0_CRC32_WIDTH 4
925 #define ID_AA64ISAR0_CRC32_VAL(x) ((x) & ID_AA64ISAR0_CRC32_MASK) argument
929 #define ID_AA64ISAR0_Atomic_WIDTH 4
931 #define ID_AA64ISAR0_Atomic_VAL(x) ((x) & ID_AA64ISAR0_Atomic_MASK) argument
935 #define ID_AA64ISAR0_TME_WIDTH 4
940 #define ID_AA64ISAR0_RDM_WIDTH 4
942 #define ID_AA64ISAR0_RDM_VAL(x) ((x) & ID_AA64ISAR0_RDM_MASK) argument
946 #define ID_AA64ISAR0_SHA3_WIDTH 4
948 #define ID_AA64ISAR0_SHA3_VAL(x) ((x) & ID_AA64ISAR0_SHA3_MASK) argument
952 #define ID_AA64ISAR0_SM3_WIDTH 4
954 #define ID_AA64ISAR0_SM3_VAL(x) ((x) & ID_AA64ISAR0_SM3_MASK) argument
958 #define ID_AA64ISAR0_SM4_WIDTH 4
960 #define ID_AA64ISAR0_SM4_VAL(x) ((x) & ID_AA64ISAR0_SM4_MASK) argument
964 #define ID_AA64ISAR0_DP_WIDTH 4
966 #define ID_AA64ISAR0_DP_VAL(x) ((x) & ID_AA64ISAR0_DP_MASK) argument
970 #define ID_AA64ISAR0_FHM_WIDTH 4
972 #define ID_AA64ISAR0_FHM_VAL(x) ((x) & ID_AA64ISAR0_FHM_MASK) argument
976 #define ID_AA64ISAR0_TS_WIDTH 4
978 #define ID_AA64ISAR0_TS_VAL(x) ((x) & ID_AA64ISAR0_TS_MASK) argument
983 #define ID_AA64ISAR0_TLB_WIDTH 4
985 #define ID_AA64ISAR0_TLB_VAL(x) ((x) & ID_AA64ISAR0_TLB_MASK) argument
990 #define ID_AA64ISAR0_RNDR_WIDTH 4
992 #define ID_AA64ISAR0_RNDR_VAL(x) ((x) & ID_AA64ISAR0_RNDR_MASK) argument
1005 #define ID_AA64ISAR1_DPB_WIDTH 4
1007 #define ID_AA64ISAR1_DPB_VAL(x) ((x) & ID_AA64ISAR1_DPB_MASK) argument
1011 #define ID_AA64ISAR1_APA_SHIFT 4
1012 #define ID_AA64ISAR1_APA_WIDTH 4
1014 #define ID_AA64ISAR1_APA_VAL(x) ((x) & ID_AA64ISAR1_APA_MASK) argument
1022 #define ID_AA64ISAR1_API_WIDTH 4
1024 #define ID_AA64ISAR1_API_VAL(x) ((x) & ID_AA64ISAR1_API_MASK) argument
1032 #define ID_AA64ISAR1_JSCVT_WIDTH 4
1034 #define ID_AA64ISAR1_JSCVT_VAL(x) ((x) & ID_AA64ISAR1_JSCVT_MASK) argument
1038 #define ID_AA64ISAR1_FCMA_WIDTH 4
1040 #define ID_AA64ISAR1_FCMA_VAL(x) ((x) & ID_AA64ISAR1_FCMA_MASK) argument
1044 #define ID_AA64ISAR1_LRCPC_WIDTH 4
1046 #define ID_AA64ISAR1_LRCPC_VAL(x) ((x) & ID_AA64ISAR1_LRCPC_MASK) argument
1051 #define ID_AA64ISAR1_GPA_WIDTH 4
1053 #define ID_AA64ISAR1_GPA_VAL(x) ((x) & ID_AA64ISAR1_GPA_MASK) argument
1057 #define ID_AA64ISAR1_GPI_WIDTH 4
1059 #define ID_AA64ISAR1_GPI_VAL(x) ((x) & ID_AA64ISAR1_GPI_MASK) argument
1063 #define ID_AA64ISAR1_FRINTTS_WIDTH 4
1065 #define ID_AA64ISAR1_FRINTTS_VAL(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK) argument
1069 #define ID_AA64ISAR1_SB_WIDTH 4
1071 #define ID_AA64ISAR1_SB_VAL(x) ((x) & ID_AA64ISAR1_SB_MASK) argument
1075 #define ID_AA64ISAR1_SPECRES_WIDTH 4
1077 #define ID_AA64ISAR1_SPECRES_VAL(x) ((x) & ID_AA64ISAR1_SPECRES_MASK) argument
1081 #define ID_AA64ISAR1_BF16_WIDTH 4
1083 #define ID_AA64ISAR1_BF16_VAL(x) ((x) & ID_AA64ISAR1_BF16_MASK) argument
1088 #define ID_AA64ISAR1_DGH_WIDTH 4
1090 #define ID_AA64ISAR1_DGH_VAL(x) ((x) & ID_AA64ISAR1_DGH_MASK) argument
1094 #define ID_AA64ISAR1_I8MM_WIDTH 4
1096 #define ID_AA64ISAR1_I8MM_VAL(x) ((x) & ID_AA64ISAR1_I8MM_MASK) argument
1100 #define ID_AA64ISAR1_XS_WIDTH 4
1102 #define ID_AA64ISAR1_XS_VAL(x) ((x) & ID_AA64ISAR1_XS_MASK) argument
1106 #define ID_AA64ISAR1_LS64_WIDTH 4
1108 #define ID_AA64ISAR1_LS64_VAL(x) ((x) & ID_AA64ISAR1_LS64_MASK) argument
1123 #define ID_AA64ISAR2_WFxT_WIDTH 4
1125 #define ID_AA64ISAR2_WFxT_VAL(x) ((x) & ID_AA64ISAR2_WFxT_MASK) argument
1128 #define ID_AA64ISAR2_RPRES_SHIFT 4
1129 #define ID_AA64ISAR2_RPRES_WIDTH 4
1131 #define ID_AA64ISAR2_RPRES_VAL(x) ((x) & ID_AA64ISAR2_RPRES_MASK) argument
1135 #define ID_AA64ISAR2_GPA3_WIDTH 4
1137 #define ID_AA64ISAR2_GPA3_VAL(x) ((x) & ID_AA64ISAR2_GPA3_MASK) argument
1141 #define ID_AA64ISAR2_APA3_WIDTH 4
1143 #define ID_AA64ISAR2_APA3_VAL(x) ((x) & ID_AA64ISAR2_APA3_MASK) argument
1151 #define ID_AA64ISAR2_MOPS_WIDTH 4
1153 #define ID_AA64ISAR2_MOPS_VAL(x) ((x) & ID_AA64ISAR2_MOPS_MASK) argument
1157 #define ID_AA64ISAR2_BC_WIDTH 4
1159 #define ID_AA64ISAR2_BC_VAL(x) ((x) & ID_AA64ISAR2_BC_MASK) argument
1163 #define ID_AA64ISAR2_PAC_frac_WIDTH 4
1165 #define ID_AA64ISAR2_PAC_frac_VAL(x) ((x) & ID_AA64ISAR2_PAC_frac_MASK) argument
1178 #define ID_AA64MMFR0_PARange_WIDTH 4
1180 #define ID_AA64MMFR0_PARange_VAL(x) ((x) & ID_AA64MMFR0_PARange_MASK) argument
1188 #define ID_AA64MMFR0_ASIDBits_SHIFT 4
1189 #define ID_AA64MMFR0_ASIDBits_WIDTH 4
1191 #define ID_AA64MMFR0_ASIDBits_VAL(x) ((x) & ID_AA64MMFR0_ASIDBits_MASK) argument
1195 #define ID_AA64MMFR0_BigEnd_WIDTH 4
1197 #define ID_AA64MMFR0_BigEnd_VAL(x) ((x) & ID_AA64MMFR0_BigEnd_MASK) argument
1201 #define ID_AA64MMFR0_SNSMem_WIDTH 4
1203 #define ID_AA64MMFR0_SNSMem_VAL(x) ((x) & ID_AA64MMFR0_SNSMem_MASK) argument
1207 #define ID_AA64MMFR0_BigEndEL0_WIDTH 4
1209 #define ID_AA64MMFR0_BigEndEL0_VAL(x) ((x) & ID_AA64MMFR0_BigEndEL0_MASK) argument
1213 #define ID_AA64MMFR0_TGran16_WIDTH 4
1215 #define ID_AA64MMFR0_TGran16_VAL(x) ((x) & ID_AA64MMFR0_TGran16_MASK) argument
1220 #define ID_AA64MMFR0_TGran64_WIDTH 4
1222 #define ID_AA64MMFR0_TGran64_VAL(x) ((x) & ID_AA64MMFR0_TGran64_MASK) argument
1226 #define ID_AA64MMFR0_TGran4_WIDTH 4
1228 #define ID_AA64MMFR0_TGran4_VAL(x) ((x) & ID_AA64MMFR0_TGran4_MASK) argument
1233 #define ID_AA64MMFR0_TGran16_2_WIDTH 4
1235 #define ID_AA64MMFR0_TGran16_2_VAL(x) ((x) & ID_AA64MMFR0_TGran16_2_MASK) argument
1241 #define ID_AA64MMFR0_TGran64_2_WIDTH 4
1243 #define ID_AA64MMFR0_TGran64_2_VAL(x) ((x) & ID_AA64MMFR0_TGran64_2_MASK) argument
1248 #define ID_AA64MMFR0_TGran4_2_WIDTH 4
1250 #define ID_AA64MMFR0_TGran4_2_VAL(x) ((x) & ID_AA64MMFR0_TGran4_2_MASK) argument
1256 #define ID_AA64MMFR0_ExS_WIDTH 4
1258 #define ID_AA64MMFR0_ExS_VAL(x) ((x) & ID_AA64MMFR0_ExS_MASK) argument
1262 #define ID_AA64MMFR0_FGT_WIDTH 4
1264 #define ID_AA64MMFR0_FGT_VAL(x) ((x) & ID_AA64MMFR0_FGT_MASK) argument
1268 #define ID_AA64MMFR0_ECV_WIDTH 4
1270 #define ID_AA64MMFR0_ECV_VAL(x) ((x) & ID_AA64MMFR0_ECV_MASK) argument
1284 #define ID_AA64MMFR1_HAFDBS_WIDTH 4
1286 #define ID_AA64MMFR1_HAFDBS_VAL(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) argument
1290 #define ID_AA64MMFR1_VMIDBits_SHIFT 4
1291 #define ID_AA64MMFR1_VMIDBits_WIDTH 4
1293 #define ID_AA64MMFR1_VMIDBits_VAL(x) ((x) & ID_AA64MMFR1_VMIDBits_MASK) argument
1297 #define ID_AA64MMFR1_VH_WIDTH 4
1299 #define ID_AA64MMFR1_VH_VAL(x) ((x) & ID_AA64MMFR1_VH_MASK) argument
1303 #define ID_AA64MMFR1_HPDS_WIDTH 4
1305 #define ID_AA64MMFR1_HPDS_VAL(x) ((x) & ID_AA64MMFR1_HPDS_MASK) argument
1310 #define ID_AA64MMFR1_LO_WIDTH 4
1312 #define ID_AA64MMFR1_LO_VAL(x) ((x) & ID_AA64MMFR1_LO_MASK) argument
1316 #define ID_AA64MMFR1_PAN_WIDTH 4
1318 #define ID_AA64MMFR1_PAN_VAL(x) ((x) & ID_AA64MMFR1_PAN_MASK) argument
1324 #define ID_AA64MMFR1_SpecSEI_WIDTH 4
1326 #define ID_AA64MMFR1_SpecSEI_VAL(x) ((x) & ID_AA64MMFR1_SpecSEI_MASK) argument
1330 #define ID_AA64MMFR1_XNX_WIDTH 4
1332 #define ID_AA64MMFR1_XNX_VAL(x) ((x) & ID_AA64MMFR1_XNX_MASK) argument
1336 #define ID_AA64MMFR1_TWED_WIDTH 4
1338 #define ID_AA64MMFR1_TWED_VAL(x) ((x) & ID_AA64MMFR1_TWED_MASK) argument
1342 #define ID_AA64MMFR1_ETS_WIDTH 4
1344 #define ID_AA64MMFR1_ETS_VAL(x) ((x) & ID_AA64MMFR1_ETS_MASK) argument
1348 #define ID_AA64MMFR1_HCX_WIDTH 4
1350 #define ID_AA64MMFR1_HCX_VAL(x) ((x) & ID_AA64MMFR1_HCX_MASK) argument
1354 #define ID_AA64MMFR1_AFP_WIDTH 4
1356 #define ID_AA64MMFR1_AFP_VAL(x) ((x) & ID_AA64MMFR1_AFP_MASK) argument
1360 #define ID_AA64MMFR1_nTLBPA_WIDTH 4
1362 #define ID_AA64MMFR1_nTLBPA_VAL(x) ((x) & ID_AA64MMFR1_nTLBPA_MASK) argument
1366 #define ID_AA64MMFR1_TIDCP1_WIDTH 4
1368 #define ID_AA64MMFR1_TIDCP1_VAL(x) ((x) & ID_AA64MMFR1_TIDCP1_MASK) argument
1372 #define ID_AA64MMFR1_CMOVW_WIDTH 4
1374 #define ID_AA64MMFR1_CMOVW_VAL(x) ((x) & ID_AA64MMFR1_CMOVW_MASK) argument
1387 #define ID_AA64MMFR2_CnP_WIDTH 4
1389 #define ID_AA64MMFR2_CnP_VAL(x) ((x) & ID_AA64MMFR2_CnP_MASK) argument
1392 #define ID_AA64MMFR2_UAO_SHIFT 4
1393 #define ID_AA64MMFR2_UAO_WIDTH 4
1395 #define ID_AA64MMFR2_UAO_VAL(x) ((x) & ID_AA64MMFR2_UAO_MASK) argument
1399 #define ID_AA64MMFR2_LSM_WIDTH 4
1401 #define ID_AA64MMFR2_LSM_VAL(x) ((x) & ID_AA64MMFR2_LSM_MASK) argument
1405 #define ID_AA64MMFR2_IESB_WIDTH 4
1407 #define ID_AA64MMFR2_IESB_VAL(x) ((x) & ID_AA64MMFR2_IESB_MASK) argument
1411 #define ID_AA64MMFR2_VARange_WIDTH 4
1413 #define ID_AA64MMFR2_VARange_VAL(x) ((x) & ID_AA64MMFR2_VARange_MASK) argument
1417 #define ID_AA64MMFR2_CCIDX_WIDTH 4
1419 #define ID_AA64MMFR2_CCIDX_VAL(x) ((x) & ID_AA64MMFR2_CCIDX_MASK) argument
1423 #define ID_AA64MMFR2_NV_WIDTH 4
1425 #define ID_AA64MMFR2_NV_VAL(x) ((x) & ID_AA64MMFR2_NV_MASK) argument
1430 #define ID_AA64MMFR2_ST_WIDTH 4
1432 #define ID_AA64MMFR2_ST_VAL(x) ((x) & ID_AA64MMFR2_ST_MASK) argument
1436 #define ID_AA64MMFR2_AT_WIDTH 4
1438 #define ID_AA64MMFR2_AT_VAL(x) ((x) & ID_AA64MMFR2_AT_MASK) argument
1442 #define ID_AA64MMFR2_IDS_WIDTH 4
1444 #define ID_AA64MMFR2_IDS_VAL(x) ((x) & ID_AA64MMFR2_IDS_MASK) argument
1448 #define ID_AA64MMFR2_FWB_WIDTH 4
1450 #define ID_AA64MMFR2_FWB_VAL(x) ((x) & ID_AA64MMFR2_FWB_MASK) argument
1454 #define ID_AA64MMFR2_TTL_WIDTH 4
1456 #define ID_AA64MMFR2_TTL_VAL(x) ((x) & ID_AA64MMFR2_TTL_MASK) argument
1460 #define ID_AA64MMFR2_BBM_WIDTH 4
1462 #define ID_AA64MMFR2_BBM_VAL(x) ((x) & ID_AA64MMFR2_BBM_MASK) argument
1467 #define ID_AA64MMFR2_EVT_WIDTH 4
1469 #define ID_AA64MMFR2_EVT_VAL(x) ((x) & ID_AA64MMFR2_EVT_MASK) argument
1474 #define ID_AA64MMFR2_E0PD_WIDTH 4
1476 #define ID_AA64MMFR2_E0PD_VAL(x) ((x) & ID_AA64MMFR2_E0PD_MASK) argument
1489 #define ID_AA64MMFR3_TCRX_WIDTH 4
1491 #define ID_AA64MMFR3_TCRX_VAL(x) ((x) & ID_AA64MMFR3_TCRX_MASK) argument
1494 #define ID_AA64MMFR3_SCTLRX_SHIFT 4
1495 #define ID_AA64MMFR3_SCTLRX_WIDTH 4
1497 #define ID_AA64MMFR3_SCTLRX_VAL(x) ((x) & ID_AA64MMFR3_SCTLRX_MASK) argument
1501 #define ID_AA64MMFR3_MEC_WIDTH 4
1503 #define ID_AA64MMFR3_MEC_VAL(x) ((x) & ID_AA64MMFR3_MEC_MASK) argument
1507 #define ID_AA64MMFR3_Spec_FPACC_WIDTH 4
1509 #define ID_AA64MMFR3_Spec_FPACC_VAL(x) ((x) & ID_AA64MMFR3_Spec_FPACC_MASK) argument
1520 #define ID_AA64MMFR4_EL1_op2 4
1528 #define ID_AA64PFR0_EL1_CRm 4
1531 #define ID_AA64PFR0_EL0_WIDTH 4
1533 #define ID_AA64PFR0_EL0_VAL(x) ((x) & ID_AA64PFR0_EL0_MASK) argument
1536 #define ID_AA64PFR0_EL1_SHIFT 4
1537 #define ID_AA64PFR0_EL1_WIDTH 4
1539 #define ID_AA64PFR0_EL1_VAL(x) ((x) & ID_AA64PFR0_EL1_MASK) argument
1543 #define ID_AA64PFR0_EL2_WIDTH 4
1545 #define ID_AA64PFR0_EL2_VAL(x) ((x) & ID_AA64PFR0_EL2_MASK) argument
1550 #define ID_AA64PFR0_EL3_WIDTH 4
1552 #define ID_AA64PFR0_EL3_VAL(x) ((x) & ID_AA64PFR0_EL3_MASK) argument
1557 #define ID_AA64PFR0_FP_WIDTH 4
1559 #define ID_AA64PFR0_FP_VAL(x) ((x) & ID_AA64PFR0_FP_MASK) argument
1564 #define ID_AA64PFR0_AdvSIMD_WIDTH 4
1566 #define ID_AA64PFR0_AdvSIMD_VAL(x) ((x) & ID_AA64PFR0_AdvSIMD_MASK) argument
1572 #define ID_AA64PFR0_GIC_WIDTH 4
1574 #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) argument
1579 #define ID_AA64PFR0_RAS_WIDTH 4
1581 #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK) argument
1586 #define ID_AA64PFR0_SVE_WIDTH 4
1588 #define ID_AA64PFR0_SVE_VAL(x) ((x) & ID_AA64PFR0_SVE_MASK) argument
1592 #define ID_AA64PFR0_SEL2_WIDTH 4
1594 #define ID_AA64PFR0_SEL2_VAL(x) ((x) & ID_AA64PFR0_SEL2_MASK) argument
1598 #define ID_AA64PFR0_MPAM_WIDTH 4
1600 #define ID_AA64PFR0_MPAM_VAL(x) ((x) & ID_AA64PFR0_MPAM_MASK) argument
1604 #define ID_AA64PFR0_AMU_WIDTH 4
1606 #define ID_AA64PFR0_AMU_VAL(x) ((x) & ID_AA64PFR0_AMU_MASK) argument
1611 #define ID_AA64PFR0_DIT_WIDTH 4
1613 #define ID_AA64PFR0_DIT_VAL(x) ((x) & ID_AA64PFR0_DIT_MASK) argument
1617 #define ID_AA64PFR0_RME_WIDTH 4
1619 #define ID_AA64PFR0_RME_VAL(x) ((x) & ID_AA64PFR0_RME_MASK) argument
1623 #define ID_AA64PFR0_CSV2_WIDTH 4
1625 #define ID_AA64PFR0_CSV2_VAL(x) ((x) & ID_AA64PFR0_CSV2_MASK) argument
1631 #define ID_AA64PFR0_CSV3_WIDTH 4
1633 #define ID_AA64PFR0_CSV3_VAL(x) ((x) & ID_AA64PFR0_CSV3_MASK) argument
1643 #define ID_AA64PFR1_EL1_CRm 4
1646 #define ID_AA64PFR1_BT_WIDTH 4
1648 #define ID_AA64PFR1_BT_VAL(x) ((x) & ID_AA64PFR1_BT_MASK) argument
1651 #define ID_AA64PFR1_SSBS_SHIFT 4
1652 #define ID_AA64PFR1_SSBS_WIDTH 4
1654 #define ID_AA64PFR1_SSBS_VAL(x) ((x) & ID_AA64PFR1_SSBS_MASK) argument
1659 #define ID_AA64PFR1_MTE_WIDTH 4
1661 #define ID_AA64PFR1_MTE_VAL(x) ((x) & ID_AA64PFR1_MTE_MASK) argument
1667 #define ID_AA64PFR1_RAS_frac_WIDTH 4
1669 #define ID_AA64PFR1_RAS_frac_VAL(x) ((x) & ID_AA64PFR1_RAS_frac_MASK) argument
1673 #define ID_AA64PFR1_MPAM_frac_WIDTH 4
1675 #define ID_AA64PFR1_MPAM_frac_VAL(x) ((x) & ID_AA64PFR1_MPAM_frac_MASK) argument
1679 #define ID_AA64PFR1_SME_WIDTH 4
1681 #define ID_AA64PFR1_SME_VAL(x) ((x) & ID_AA64PFR1_SME_MASK) argument
1686 #define ID_AA64PFR1_RNDR_trap_WIDTH 4
1688 #define ID_AA64PFR1_RNDR_trap_VAL(x) ((x) & ID_AA64PFR1_RNDR_trap_MASK) argument
1692 #define ID_AA64PFR1_CSV2_frac_WIDTH 4
1694 #define ID_AA64PFR1_CSV2_frac_VAL(x) ((x) & ID_AA64PFR1_CSV2_frac_MASK) argument
1699 #define ID_AA64PFR1_NMI_WIDTH 4
1701 #define ID_AA64PFR1_NMI_VAL(x) ((x) & ID_AA64PFR1_NMI_MASK) argument
1711 #define ID_AA64PFR2_EL1_CRm 4
1720 #define ID_AA64ZFR0_EL1_CRm 4
1721 #define ID_AA64ZFR0_EL1_op2 4
1723 #define ID_AA64ZFR0_SVEver_WIDTH 4
1725 #define ID_AA64ZFR0_SVEver_VAL(x) ((x) & ID_AA64ZFR0_SVEver_MASK argument
1729 #define ID_AA64ZFR0_AES_SHIFT 4
1730 #define ID_AA64ZFR0_AES_WIDTH 4
1732 #define ID_AA64ZFR0_AES_VAL(x) ((x) & ID_AA64ZFR0_AES_MASK argument
1737 #define ID_AA64ZFR0_BitPerm_WIDTH 4
1739 #define ID_AA64ZFR0_BitPerm_VAL(x) ((x) & ID_AA64ZFR0_BitPerm_MASK argument
1743 #define ID_AA64ZFR0_BF16_WIDTH 4
1745 #define ID_AA64ZFR0_BF16_VAL(x) ((x) & ID_AA64ZFR0_BF16_MASK argument
1750 #define ID_AA64ZFR0_SHA3_WIDTH 4
1752 #define ID_AA64ZFR0_SHA3_VAL(x) ((x) & ID_AA64ZFR0_SHA3_MASK argument
1756 #define ID_AA64ZFR0_SM4_WIDTH 4
1758 #define ID_AA64ZFR0_SM4_VAL(x) ((x) & ID_AA64ZFR0_SM4_MASK argument
1762 #define ID_AA64ZFR0_I8MM_WIDTH 4
1764 #define ID_AA64ZFR0_I8MM_VAL(x) ((x) & ID_AA64ZFR0_I8MM_MASK argument
1768 #define ID_AA64ZFR0_F32MM_WIDTH 4
1770 #define ID_AA64ZFR0_F32MM_VAL(x) ((x) & ID_AA64ZFR0_F32MM_MASK argument
1774 #define ID_AA64ZFR0_F64MM_WIDTH 4
1776 #define ID_AA64ZFR0_F64MM_VAL(x) ((x) & ID_AA64ZFR0_F64MM_MASK argument
1788 #define ID_ISAR5_SEVL_WIDTH 4
1790 #define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK) argument
1793 #define ID_ISAR5_AES_SHIFT 4
1794 #define ID_ISAR5_AES_WIDTH 4
1796 #define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK) argument
1801 #define ID_ISAR5_SHA1_WIDTH 4
1803 #define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK) argument
1807 #define ID_ISAR5_SHA2_WIDTH 4
1809 #define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK) argument
1813 #define ID_ISAR5_CRC32_WIDTH 4
1815 #define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK) argument
1819 #define ID_ISAR5_RDM_WIDTH 4
1821 #define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK) argument
1825 #define ID_ISAR5_VCMA_WIDTH 4
1827 #define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK) argument
1901 #define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK) argument
1904 #define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK) argument
1907 #define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK) argument
1914 #define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK) argument
1924 #define MVFR0_SIMDReg_WIDTH 4
1926 #define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK) argument
1930 #define MVFR0_FPSP_SHIFT 4
1931 #define MVFR0_FPSP_WIDTH 4
1933 #define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK) argument
1938 #define MVFR0_FPDP_WIDTH 4
1940 #define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK) argument
1945 #define MVFR0_FPTrap_WIDTH 4
1947 #define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK) argument
1951 #define MVFR0_FPDivide_WIDTH 4
1953 #define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK) argument
1957 #define MVFR0_FPSqrt_WIDTH 4
1959 #define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK) argument
1963 #define MVFR0_FPShVec_WIDTH 4
1965 #define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK) argument
1969 #define MVFR0_FPRound_WIDTH 4
1971 #define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK) argument
1983 #define MVFR1_FPFtZ_WIDTH 4
1985 #define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK) argument
1988 #define MVFR1_FPDNaN_SHIFT 4
1989 #define MVFR1_FPDNaN_WIDTH 4
1991 #define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK) argument
1995 #define MVFR1_SIMDLS_WIDTH 4
1997 #define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK) argument
2001 #define MVFR1_SIMDInt_WIDTH 4
2003 #define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK) argument
2007 #define MVFR1_SIMDSP_WIDTH 4
2009 #define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK) argument
2013 #define MVFR1_SIMDHP_WIDTH 4
2015 #define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK) argument
2020 #define MVFR1_FPHP_WIDTH 4
2022 #define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK) argument
2028 #define MVFR1_SIMDFMAC_WIDTH 4
2030 #define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK) argument
2040 #define OSDLR_EL1_op2 4
2048 #define OSLAR_EL1_op2 4
2056 #define OSLSR_EL1_op2 4
2061 #define PAR_SUCCESS(x) (((x) & PAR_F) == 0) argument
2090 #define PMBIDR_P_SHIFT 4
2207 #define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
2312 #define PMSCR_PA_SHIFT 4
2344 #define PMSFCR_EL1_op2 4
2389 #define PMSIDR_LDS_SHIFT 4
2445 #define PMSWINC_EL0_op2 4
2477 #define RNDRRS_CRm 4
2492 #define SCTLR_SA0 (UL(0x1) << 4)
2549 #define SPSR_EL1_CRn 4
2602 #define SPSR_EL12_CRn 4
2682 #define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT)
2701 #define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT) argument
2718 #define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT) argument
2719 #define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x)) argument
2794 #define ZCR_LEN_BYTES(x) ((((x) & ZCR_LEN_MASK) + 1) * 16) argument