Lines Matching +full:0 +full:x1040
38 #define GENET_SYS_REV_CTRL 0x000
41 #define REV_MAJOR 0xf000000
44 #define REV_MINOR 0xf0000
46 #define REV_PHY 0xffff
47 #define GENET_SYS_PORT_CTRL 0x004
49 #define GENET_SYS_RBUF_FLUSH_CTRL 0x008
51 #define GENET_SYS_TBUF_FLUSH_CTRL 0x00c
52 #define GENET_EXT_RGMII_OOB_CTRL 0x08c
57 #define GENET_INTRL2_CPU_STAT 0x200
58 #define GENET_INTRL2_CPU_CLEAR 0x208
59 #define GENET_INTRL2_CPU_STAT_MASK 0x20c
60 #define GENET_INTRL2_CPU_SET_MASK 0x210
61 #define GENET_INTRL2_CPU_CLEAR_MASK 0x214
66 #define GENET_RBUF_CTRL 0x300
69 #define GENET_RBUF_64B_EN __BIT(0)
70 #define GENET_RBUF_CHECK_CTRL 0x314
71 #define GENET_RBUF_CHECK_CTRL_EN __BIT(0)
73 #define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4
74 #define GENET_TBUF_CTRL 0x600
75 #define GENET_UMAC_CMD 0x808
81 #define GENET_UMAC_CMD_SPEED_10 0
86 #define GENET_UMAC_CMD_SPEED_10 (0 << 2)
92 #define GENET_UMAC_CMD_TXEN __BIT(0)
93 #define GENET_UMAC_MAC0 0x80c
94 #define GENET_UMAC_MAC1 0x810
95 #define GENET_UMAC_MAX_FRAME_LEN 0x814
96 #define GENET_UMAC_TX_FLUSH 0xb34
97 #define GENET_UMAC_MIB_CTRL 0xd80
100 #define GENET_UMAC_MIB_RESET_RX __BIT(0)
101 #define GENET_MDIO_CMD 0xe14
110 #define GENET_MDIO_VAL_MASK 0xffff
111 #define GENET_UMAC_MDF_CTRL 0xe50
112 #define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8)
113 #define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8)
120 #define GENET_DMA_RING_SIZE 0x40
123 #define GENET_RX_BASE 0x2000
124 #define GENET_TX_BASE 0x4000
126 #define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid))
127 #define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00)
128 #define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04)
129 #define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08)
130 #define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c)
131 #define GENET_RX_DMA_PROD_CONS_MASK 0xffff
132 #define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10)
134 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0)
136 #define GENET_RX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff
137 #define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14)
138 #define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18)
139 #define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c)
140 #define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20)
141 #define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28)
143 #define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0)
145 #define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c)
146 #define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30)
148 #define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid))
149 #define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00)
150 #define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04)
151 #define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08)
152 #define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c)
153 #define GENET_TX_DMA_PROD_CONS_MASK 0xffff
154 #define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10)
156 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0)
158 #define GENET_TX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff
159 #define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14)
160 #define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18)
161 #define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c)
162 #define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20)
163 #define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24)
164 #define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28)
165 #define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c)
166 #define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30)
168 #define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00)
170 #define GENET_RX_DESC_STATUS_BUFLEN_MASK 0xfff0000
177 #define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04)
178 #define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08)
180 #define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00)
189 #define GENET_TX_DESC_STATUS_BUFLEN_MASK 0x7ff0000
190 #define GENET_TX_DESC_STATUS_QTAG_MASK 0x1f80
191 #define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04)
192 #define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08)
209 #define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00)
210 #define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04)
212 #define GENET_RX_DMA_CTRL_EN __BIT(0)
213 #define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c)
215 #define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00)
216 #define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04)
218 #define GENET_TX_DMA_CTRL_EN __BIT(0)
219 #define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c)