691 gen_init_txring(struct gen_softc *sc, int queue, int qid, int base,  in gen_init_txring()  argument
699 	q->hwindex = qid;  in gen_init_txring()
709 	WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);  in gen_init_txring()
710 	WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);  in gen_init_txring()
711 	WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);  in gen_init_txring()
712 	WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);  in gen_init_txring()
713 	WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),  in gen_init_txring()
716 	WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);  in gen_init_txring()
717 	WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);  in gen_init_txring()
718 	WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),  in gen_init_txring()
720 	WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);  in gen_init_txring()
721 	WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), 1);  in gen_init_txring()
722 	WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);  in gen_init_txring()
723 	WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);  in gen_init_txring()
724 	WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);  in gen_init_txring()
726 	WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid));	/* enable */  in gen_init_txring()
731 	val |= GENET_TX_DMA_CTRL_RBUF_EN(qid);  in gen_init_txring()
740 gen_init_rxring(struct gen_softc *sc, int queue, int qid, int base,  in gen_init_rxring()  argument
749 	q->hwindex = qid;  in gen_init_rxring()
755 	WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);  in gen_init_rxring()
756 	WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);  in gen_init_rxring()
757 	WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);  in gen_init_rxring()
758 	WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);  in gen_init_rxring()
759 	WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),  in gen_init_rxring()
762 	WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);  in gen_init_rxring()
763 	WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);  in gen_init_rxring()
764 	WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),  in gen_init_rxring()
766 	WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);  in gen_init_rxring()
767 	WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),  in gen_init_rxring()
769 	WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);  in gen_init_rxring()
770 	WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);  in gen_init_rxring()
772 	WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid));	/* enable */  in gen_init_rxring()
781 	val |= GENET_RX_DMA_CTRL_RBUF_EN(qid);  in gen_init_rxring()