Lines Matching +full:0 +full:x3f
43 #define ZY7_SCLR_SCL 0x0000
44 #define ZY7_SLCR_LOCK 0x0004
45 #define ZY7_SLCR_LOCK_MAGIC 0x767b
46 #define ZY7_SLCR_UNLOCK 0x0008
47 #define ZY7_SLCR_UNLOCK_MAGIC 0xdf0d
48 #define ZY7_SLCR_LOCKSTA 0x000c
51 #define ZY7_SLCR_ARM_PLL_CTRL 0x0100
52 #define ZY7_SLCR_DDR_PLL_CTRL 0x0104
53 #define ZY7_SLCR_IO_PLL_CTRL 0x0108
54 #define ZY7_SLCR_PLL_CTRL_RESET (1 << 0)
59 #define ZY7_SLCR_PLL_CTRL_FDIV_MASK (0x7f << 12)
60 #define ZY7_SLCR_PLL_STATUS 0x010c
61 #define ZY7_SLCR_PLL_STAT_ARM_PLL_LOCK (1 << 0)
67 #define ZY7_SLCR_ARM_PLL_CFG 0x0110
68 #define ZY7_SLCR_DDR_PLL_CFG 0x0114
69 #define ZY7_SLCR_IO_PLL_CFG 0x0118
71 #define ZY7_SLCR_PLL_CFG_RES_MASK (0xf << 4)
73 #define ZY7_SLCR_PLL_CFG_PLL_CP_MASK (0xf << 8)
75 #define ZY7_SLCR_PLL_CFG_LOCK_CNT_MASK (0x3ff << 12)
78 #define ZY7_SLCR_ARM_CLK_CTRL 0x0120
85 #define ZY7_SLCR_ARM_CLK_CTRL_SRCSEL_ARM_PLL (0 << 4)
89 #define ZY7_SLCR_ARM_CLK_CTRL_DIVISOR_MASK (0x3f << 8)
90 #define ZY7_SLCR_DDR_CLK_CTRL 0x0124
92 #define ZY7_SLCR_DDR_CLK_CTRL_2XCLK_DIV_MASK (0x3f << 26)
94 #define ZY7_SLCR_DDR_CLK_CTRL_3XCLK_DIV_MASK (0x3f << 20)
96 #define ZY7_SLCR_DDR_CLK_CTRL_3XCLKACT (1 << 0)
97 #define ZY7_SLCR_DCI_CLK_CTRL 0x0128
99 #define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR1_MASK (0x3f << 20)
101 #define ZY7_SLCR_DCI_CLK_CTRL_DIVISOR0_MASK (0x3f << 8)
102 #define ZY7_SLCR_DCI_CLK_CTRL_CLKACT (1 << 0)
103 #define ZY7_SLCR_APER_CLK_CTRL 0x012c /* amba periph clk ctrl */
121 #define ZY7_SLCR_APER_CLK_CTRL_DMA_CPU_1XCLKACT (1 << 0)
122 #define ZY7_SLCR_USB0_CLK_CTRL 0x0130
123 #define ZY7_SLCR_USB1_CLK_CTRL 0x0134
124 #define ZY7_SLCR_GEM0_RCLK_CTRL 0x0138
125 #define ZY7_SLCR_GEM1_RCLK_CTRL 0x013c
126 #define ZY7_SLCR_GEM0_CLK_CTRL 0x0140
127 #define ZY7_SLCR_GEM1_CLK_CTRL 0x0144
128 #define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MASK (0x3f << 20)
130 #define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR1_MAX 0x3f
131 #define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MASK (0x3f << 8)
133 #define ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX 0x3f
135 #define ZY7_SLCR_GEM_CLK_CTRL_SRCSEL_IO_PLL (0 << 4)
140 #define ZY7_SLCR_SMC_CLK_CTRL 0x0148
141 #define ZY7_SLCR_LQSPI_CLK_CTRL 0x014c
142 #define ZY7_SLCR_SDIO_CLK_CTRL 0x0150
143 #define ZY7_SLCR_UART_CLK_CTRL 0x0154
144 #define ZY7_SLCR_SPI_CLK_CTRL 0x0158
145 #define ZY7_SLCR_CAN_CLK_CTRL 0x015c
146 #define ZY7_SLCR_CAN_MIOCLK_CTRL 0x0160
147 #define ZY7_SLCR_DBG_CLK_CTRL 0x0164
148 #define ZY7_SLCR_PCAP_CLK_CTRL 0x0168
149 #define ZY7_SLCR_TOPSW_CLK_CTRL 0x016c /* central intercnn clk ctrl */
150 #define ZY7_SLCR_FPGA_CLK_CTRL(unit) (0x0170 + 0x10 * (unit))
152 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK (0x3f << 20)
154 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK (0x3f << 8)
155 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX 0x3f
158 #define ZY7_SLCR_FPGA_THR_CTRL(unit) (0x0174 + 0x10 * (unit))
160 #define ZY7_SLCR_FPGA_THR_CTRL_CPU_START (1 << 0)
161 #define ZY7_SLCR_FPGA_THR_CNT(unit) (0x0178 + 0x10 * (unit))
162 #define ZY7_SLCR_FPGA_THR_STA(unit) (0x017c + 0x10 * (unit))
163 #define ZY7_SLCR_CLK_621_TRUE 0x01c4 /* cpu clock ratio mode */
166 #define ZY7_SLCR_PSS_RST_CTRL 0x0200
167 #define ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET (1 << 0)
168 #define ZY7_SLCR_DDR_RST_CTRL 0x0204
169 #define ZY7_SLCR_TOPSW_RST_CTRL 0x0208
170 #define ZY7_SLCR_DMAC_RST_CTRL 0x020c
171 #define ZY7_SLCR_USB_RST_CTRL 0x0210
172 #define ZY7_SLCR_GEM_RST_CTRL 0x0214
173 #define ZY7_SLCR_SDIO_RST_CTRL 0x0218
174 #define ZY7_SLCR_SPI_RST_CTRL 0x021c
175 #define ZY7_SLCR_CAN_RST_CTRL 0x0220
176 #define ZY7_SLCR_I2C_RST_CTRL 0x0224
177 #define ZY7_SLCR_UART_RST_CTRL 0x0228
178 #define ZY7_SLCR_GPIO_RST_CTRL 0x022c
179 #define ZY7_SLCR_LQSPI_RST_CTRL 0x0230
180 #define ZY7_SLCR_SMC_RST_CTRL 0x0234
181 #define ZY7_SLCR_OCM_RST_CTRL 0x0238
182 #define ZY7_SLCR_DEVCI_RST_CTRL 0x023c
183 #define ZY7_SLCR_FPGA_RST_CTRL 0x0240
187 #define ZY7_SLCR_FPGA_RST_CTRL_FPGA0_OUT_RST (1 << 0)
188 #define ZY7_SLCR_FPGA_RST_CTRL_RST_ALL 0xf
189 #define ZY7_SLCR_A9_CPU_RST_CTRL 0x0244
190 #define ZY7_SLCR_RS_AWDT_CTRL 0x024c
192 #define ZY7_SLCR_REBOOT_STAT 0x0258
193 #define ZY7_SLCR_REBOOT_STAT_STATE_MASK (0xffU << 24)
201 #define ZY7_SLCR_REBOOT_STAT_BOOTROM_ERR_CODE_MASK (0xffff)
202 #define ZY7_SLCR_BOOT_MODE 0x025c
206 #define ZY7_SLCR_BOOT_MODE_BOOTDEV_JTAG 0
211 #define ZY7_SLCR_APU_CTRL 0x0300
212 #define ZY7_SLCR_WDT_CLK_SEL 0x0304
214 #define ZY7_SLCR_PSS_IDCODE 0x0530
215 #define ZY7_SLCR_PSS_IDCODE_REVISION_MASK (0xfU << 28)
217 #define ZY7_SLCR_PSS_IDCODE_FAMILY_MASK (0x7f << 21)
219 #define ZY7_SLCR_PSS_IDCODE_SUB_FAMILY_MASK (0xf << 17)
221 #define ZY7_SLCR_PSS_IDCODE_DEVICE_MASK (0x1f << 12)
222 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z007S (0x03 << 12)
223 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z010 (0x02 << 12)
224 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z012S (0x1c << 12)
225 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z014S (0x08 << 12)
226 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z015 (0x1b << 12)
227 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z020 (0x07 << 12)
228 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z030 (0x0c << 12)
229 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z045 (0x11 << 12)
230 #define ZY7_SLCR_PSS_IDCODE_DEVICE_7Z100 (0x16 << 12)
232 #define ZY7_SLCR_PSS_IDCODE_MNFR_ID_MASK (0x7ff << 1)
235 #define ZY7_SLCR_DDR_URGENT 0x0600
236 #define ZY7_SLCR_DDR_CAL_START 0x060c
237 #define ZY7_SLCR_DDR_REF_START 0x0614
238 #define ZY7_SLCR_DDR_CMD_STA 0x0618
239 #define ZY7_SLCR_DDR_URGENT_SEL 0x061c
240 #define ZY7_SLCR_DDR_DFI_STATUS 0x0620
243 #define ZY7_SLCR_MIO_PIN(n) (0x0700 + (n) * 4) /* 0-53 */
247 #define ZY7_SLCR_MIO_PIN_IO_TYPE_LVTTL (0 << 9)
253 #define ZY7_SLCR_MIO_PIN_L2_SEL_L3_MUX (0 << 3)
259 #define ZY7_SLCR_MIO_PIN_TRI_EN (1 << 0)
261 #define ZY7_SLCR_MIO_LOOPBACK 0x0804
265 #define ZY7_SLCR_MIO_LOOPBACK_SPI0_SPI1 (1 << 0)
266 #define ZY7_SLCR_MIO_MST_TRI0 0x080c
267 #define ZY7_SLCR_MIO_MST_TRI1 0x0810
268 #define ZY7_SLCR_SD0_WP_CD_SEL 0x0830
269 #define ZY7_SLCR_SD1_WP_CD_SEL 0x0834
272 #define ZY7_SLCR_LVL_SHFTR_EN 0x900
276 #define ZY7_SLCR_LVL_SHFTR_EN_USER_LVL_OUT_EN_1 (1 << 0) /* PS to PL */
277 #define ZY7_SLCR_LVL_SHFTR_EN_ALL 0xf
279 #define ZY7_SLCR_OCM_CFG 0x0910
281 #define ZY7_SLCR_GPIOB_CTRL 0x0b00
282 #define ZY7_SLCR_GPIOB_CFG_CMOS18 0x0b04
283 #define ZY7_SLCR_GPIOB_CFG_CMOS25 0x0b08
284 #define ZY7_SLCR_GPIOB_CFG_CMOS33 0x0b0c
285 #define ZY7_SLCR_GPIOB_CFG_LVTTL 0x0b10
286 #define ZY7_SLCR_GPIOB_CFG_HSTL 0x0b14
287 #define ZY7_SLCR_GPIOB_DRVR_BIAS_CTRL 0x0b18
289 #define ZY7_SLCR_DDRIOB_ADDR0 0x0b40
290 #define ZY7_SLCR_DDRIOB_ADDR1 0x0b44
291 #define ZY7_SLCR_DDRIOB_DATA0 0x0b48
292 #define ZY7_SLCR_DDRIOB_DATA1 0x0b4c
293 #define ZY7_SLCR_DDRIOB_DIFF0 0x0b50
294 #define ZY7_SLCR_DDRIOB_DIFF1 0x0b54
295 #define ZY7_SLCR_DDRIOB_CLK 0x0b58
296 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_ADDR 0x0b5c
297 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DATA 0x0b60
298 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_DIFF 0x0b64
299 #define ZY7_SLCR_DDRIOB_DRIVE_SLEW_CLK 0x0b68
300 #define ZY7_SLCR_DDRIOB_DDR_CTRL 0x0b6c
301 #define ZY7_SLCR_DDRIOB_DCI_CTRL 0x0b70
302 #define ZY7_SLCR_DDRIOB_DCI_STATUS 0x0b74
310 #define ZY7_PL_FCLK_SRC_IO 0