Lines Matching refs:div0
213 int div0, div1; in cgem_set_ref_clk() local
222 div0 = (io_pll_frequency + div1 * frequency / 2) / in cgem_set_ref_clk()
224 if (div0 > 0 && div0 <= ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_MAX && in cgem_set_ref_clk()
225 ((io_pll_frequency / div0 / div1) + 500) / 1000 == in cgem_set_ref_clk()
241 (div0 << ZY7_SLCR_GEM_CLK_CTRL_DIVISOR_SHIFT) | in cgem_set_ref_clk()
314 int div0, div1; in zy7_pl_fclk_set_freq() local
344 div0 = (base_frequency + div1 * frequency / 2) / in zy7_pl_fclk_set_freq()
346 if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX && in zy7_pl_fclk_set_freq()
347 ((base_frequency / div0 / div1) + 500) / 1000 == in zy7_pl_fclk_set_freq()
365 (div0 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_SHIFT); in zy7_pl_fclk_set_freq()
373 return (base_frequency / div0 / div1); in zy7_pl_fclk_set_freq()
380 int div0, div1; in zy7_pl_fclk_get_freq() local
413 div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >> in zy7_pl_fclk_get_freq()
418 if (div0 == 0) in zy7_pl_fclk_get_freq()
419 div0 = 1; in zy7_pl_fclk_get_freq()
424 frequency = (base_frequency / div0 / div1); in zy7_pl_fclk_get_freq()