Lines Matching +full:positive +full:- +full:reference +full:- +full:buffer

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 * Zynq-7000 Devcfg driver. This allows programming the PL (FPGA) section
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
88 #define DEVCFG_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
89 #define DEVCFG_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
91 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
93 #define DEVCFG_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx);
94 #define DEVCFG_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED);
96 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
97 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
100 "Xilinx Zynq-7000 PL (FPGA) section");
111 "Enable PS-PL level shifters after device config");
115 "Zynq-7000 PS version");
227 #define ZY7_DEVCFG_DMA_SRC_LEN 0x020 /* in 4-byte words. */
259 switch (cfg->source) { in zy7_devcfg_fclk_sysctl_source()
276 if (error != 0 || req->newptr == NULL) in zy7_devcfg_fclk_sysctl_source()
280 cfg->source = ZY7_PL_FCLK_SRC_IO; in zy7_devcfg_fclk_sysctl_source()
282 cfg->source = ZY7_PL_FCLK_SRC_DDR; in zy7_devcfg_fclk_sysctl_source()
284 cfg->source = ZY7_PL_FCLK_SRC_ARM; in zy7_devcfg_fclk_sysctl_source()
288 zy7_pl_fclk_set_source(unit, cfg->source); in zy7_devcfg_fclk_sysctl_source()
289 if (cfg->frequency > 0) in zy7_devcfg_fclk_sysctl_source()
290 cfg->actual_frequency = zy7_pl_fclk_get_freq(unit); in zy7_devcfg_fclk_sysctl_source()
307 freq = cfg->frequency; in zy7_devcfg_fclk_sysctl_freq()
310 if (error != 0 || req->newptr == NULL) in zy7_devcfg_fclk_sysctl_freq()
325 cfg->frequency = freq; in zy7_devcfg_fclk_sysctl_freq()
326 cfg->actual_frequency = new_actual_freq; in zy7_devcfg_fclk_sysctl_freq()
339 if (error != 0 || req->newptr == NULL) in zy7_devcfg_fclk_sysctl_level_shifters()
357 sysctl_ctx_init(&sc->sysctl_tree); in zy7_devcfg_init_fclk_sysctl()
358 sc->sysctl_tree_top = SYSCTL_ADD_NODE(&sc->sysctl_tree, in zy7_devcfg_init_fclk_sysctl()
361 if (sc->sysctl_tree_top == NULL) { in zy7_devcfg_init_fclk_sysctl()
362 sysctl_ctx_free(&sc->sysctl_tree); in zy7_devcfg_init_fclk_sysctl()
363 return (-1); in zy7_devcfg_init_fclk_sysctl()
368 fclk_node = SYSCTL_ADD_NODE(&sc->sysctl_tree, in zy7_devcfg_init_fclk_sysctl()
369 SYSCTL_CHILDREN(sc->sysctl_tree_top), OID_AUTO, fclk_num, in zy7_devcfg_init_fclk_sysctl()
372 SYSCTL_ADD_INT(&sc->sysctl_tree, in zy7_devcfg_init_fclk_sysctl()
377 SYSCTL_ADD_PROC(&sc->sysctl_tree, in zy7_devcfg_init_fclk_sysctl()
383 SYSCTL_ADD_PROC(&sc->sysctl_tree, in zy7_devcfg_init_fclk_sysctl()
430 /* Clear sticky bits and set up INIT signal positive edge interrupt. */ in zy7_devcfg_reset_pl()
448 /* Wait for positive edge interrupt. */ in zy7_devcfg_reset_pl()
449 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i1", hz); in zy7_devcfg_reset_pl()
467 /* Clear sticky bits and set up INIT positive edge interrupt. */ in zy7_devcfg_reset_pl()
479 err = mtx_sleep(sc, &sc->sc_mtx, PCATCH, "zy7i2", hz); in zy7_devcfg_reset_pl()
500 struct zy7_devcfg_softc *sc = dev->si_drv1; in zy7_devcfg_open()
504 if (sc->is_open) { in zy7_devcfg_open()
509 sc->dma_map = NULL; in zy7_devcfg_open()
510 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 4, 0, in zy7_devcfg_open()
519 &sc->sc_mtx, in zy7_devcfg_open()
520 &sc->dma_tag); in zy7_devcfg_open()
526 sc->is_open = 1; in zy7_devcfg_open()
534 struct zy7_devcfg_softc *sc = dev->si_drv1; in zy7_devcfg_write()
542 if (uio->uio_offset == 0 && uio->uio_resid > 0) { in zy7_devcfg_write()
553 err = bus_dmamem_alloc(sc->dma_tag, &dma_mem, BUS_DMA_NOWAIT, in zy7_devcfg_write()
554 &sc->dma_map); in zy7_devcfg_write()
559 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, dma_mem, PAGE_SIZE, in zy7_devcfg_write()
562 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map); in zy7_devcfg_write()
567 while (uio->uio_resid > 0) { in zy7_devcfg_write()
575 /* uiomove the data from user buffer to our dma map. */ in zy7_devcfg_write()
576 segsz = MIN(PAGE_SIZE, uio->uio_resid); in zy7_devcfg_write()
584 bus_dmamap_sync(sc->dma_tag, sc->dma_map, in zy7_devcfg_write()
590 if (uio->uio_resid > segsz) in zy7_devcfg_write()
606 err = mtx_sleep(sc->dma_map, &sc->sc_mtx, PCATCH, in zy7_devcfg_write()
611 bus_dmamap_sync(sc->dma_tag, sc->dma_map, in zy7_devcfg_write()
620 bus_dmamap_unload(sc->dma_tag, sc->dma_map); in zy7_devcfg_write()
621 bus_dmamem_free(sc->dma_tag, dma_mem, sc->dma_map); in zy7_devcfg_write()
629 struct zy7_devcfg_softc *sc = dev->si_drv1; in zy7_devcfg_close()
632 sc->is_open = 0; in zy7_devcfg_close()
633 bus_dma_tag_destroy(sc->dma_tag); in zy7_devcfg_close()
662 wakeup(sc->dma_map); in zy7_devcfg_intr()
664 /* INIT_B positive edge? */ in zy7_devcfg_intr()
719 sc->dev = dev; in zy7_devcfg_attach()
725 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in zy7_devcfg_attach()
727 if (sc->mem_res == NULL) { in zy7_devcfg_attach()
735 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in zy7_devcfg_attach()
737 if (sc->irq_res == NULL) { in zy7_devcfg_attach()
744 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, in zy7_devcfg_attach()
745 NULL, zy7_devcfg_intr, sc, &sc->intrhandle); in zy7_devcfg_attach()
753 sc->sc_ctl_dev = make_dev(&zy7_devcfg_cdevsw, 0, in zy7_devcfg_attach()
755 if (sc->sc_ctl_dev == NULL) { in zy7_devcfg_attach()
760 sc->sc_ctl_dev->si_drv1 = sc; in zy7_devcfg_attach()
800 if (sc->sysctl_tree_top != NULL) { in zy7_devcfg_detach()
801 sysctl_ctx_free(&sc->sysctl_tree); in zy7_devcfg_detach()
802 sc->sysctl_tree_top = NULL; in zy7_devcfg_detach()
806 if (sc->sc_ctl_dev != NULL) in zy7_devcfg_detach()
807 destroy_dev(sc->sc_ctl_dev); in zy7_devcfg_detach()
810 if (sc->irq_res != NULL) { in zy7_devcfg_detach()
811 if (sc->intrhandle) in zy7_devcfg_detach()
812 bus_teardown_intr(dev, sc->irq_res, sc->intrhandle); in zy7_devcfg_detach()
814 rman_get_rid(sc->irq_res), sc->irq_res); in zy7_devcfg_detach()
818 if (sc->mem_res != NULL) in zy7_devcfg_detach()
820 rman_get_rid(sc->mem_res), sc->mem_res); in zy7_devcfg_detach()