Lines Matching +full:cs +full:- +full:x
1 /*-
84 device_printf(dev, "SYSCONFIG: %#x\n", reg); in ti_spi_printr()
86 device_printf(dev, "SYSSTATUS: %#x\n", reg); in ti_spi_printr()
88 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); in ti_spi_printr()
90 device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS); in ti_spi_printr()
92 device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS); in ti_spi_printr()
93 for (i = 0; i < sc->sc_numcs; i++) { in ti_spi_printr()
96 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); in ti_spi_printr()
103 while (j-- > 0) in ti_spi_printr()
108 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); in ti_spi_printr()
110 device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS); in ti_spi_printr()
111 device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS); in ti_spi_printr()
114 device_printf(dev, "XFERLEVEL: %#x\n", reg); in ti_spi_printr()
155 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) in ti_spi_probe()
171 sc->sc_dev = dev; in ti_spi_attach()
181 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", in ti_spi_attach()
182 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { in ti_spi_attach()
183 sc->sc_numcs = 2; in ti_spi_attach()
187 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in ti_spi_attach()
189 if (!sc->sc_mem_res) { in ti_spi_attach()
194 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); in ti_spi_attach()
195 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); in ti_spi_attach()
198 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in ti_spi_attach()
200 if (!sc->sc_irq_res) { in ti_spi_attach()
201 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in ti_spi_attach()
207 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, in ti_spi_attach()
208 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { in ti_spi_attach()
209 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); in ti_spi_attach()
210 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in ti_spi_attach()
215 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); in ti_spi_attach()
222 if (--timeout == 0) { in ti_spi_attach()
235 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", in ti_spi_attach()
250 for (i = 0; i < sc->sc_numcs; i++) { in ti_spi_attach()
252 * Default to SPI mode 0, CS active low, 8 bits word length and in ti_spi_attach()
257 (8 - 1) << MCSPI_CONF_WL_SHIFT); in ti_spi_attach()
258 /* Set initial clock - 500kHz. */ in ti_spi_attach()
291 mtx_destroy(&sc->sc_mtx); in ti_spi_detach()
292 if (sc->sc_intrhand) in ti_spi_detach()
293 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); in ti_spi_detach()
294 if (sc->sc_irq_res) in ti_spi_detach()
295 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); in ti_spi_detach()
296 if (sc->sc_mem_res) in ti_spi_detach()
297 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); in ti_spi_detach()
310 cmd = sc->sc_cmd; in ti_spi_fill_fifo()
311 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); in ti_spi_fill_fifo()
312 while (bytes-- > 0) { in ti_spi_fill_fifo()
313 data = (uint8_t *)cmd->tx_cmd; in ti_spi_fill_fifo()
314 written = sc->sc_written++; in ti_spi_fill_fifo()
315 if (written >= cmd->tx_cmd_sz) { in ti_spi_fill_fifo()
316 data = (uint8_t *)cmd->tx_data; in ti_spi_fill_fifo()
317 written -= cmd->tx_cmd_sz; in ti_spi_fill_fifo()
319 if (sc->sc_fifolvl == 1) { in ti_spi_fill_fifo()
322 while (--timeout > 0 && (TI_SPI_READ(sc, in ti_spi_fill_fifo()
323 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { in ti_spi_fill_fifo()
327 return (-1); in ti_spi_fill_fifo()
329 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); in ti_spi_fill_fifo()
343 cmd = sc->sc_cmd; in ti_spi_drain_fifo()
344 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); in ti_spi_drain_fifo()
345 while (bytes-- > 0) { in ti_spi_drain_fifo()
346 data = (uint8_t *)cmd->rx_cmd; in ti_spi_drain_fifo()
347 read = sc->sc_read++; in ti_spi_drain_fifo()
348 if (read >= cmd->rx_cmd_sz) { in ti_spi_drain_fifo()
349 data = (uint8_t *)cmd->rx_data; in ti_spi_drain_fifo()
350 read -= cmd->rx_cmd_sz; in ti_spi_drain_fifo()
352 if (sc->sc_fifolvl == 1) { in ti_spi_drain_fifo()
355 while (--timeout > 0 && (TI_SPI_READ(sc, in ti_spi_drain_fifo()
356 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { in ti_spi_drain_fifo()
360 return (-1); in ti_spi_drain_fifo()
362 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); in ti_spi_drain_fifo()
393 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { in ti_spi_intr()
394 sc->sc_flags |= TI_SPI_DONE; in ti_spi_intr()
395 wakeup(sc->sc_dev); in ti_spi_intr()
405 while (sc->sc_len - sc->sc_written > 0) { in ti_spi_pio_transfer()
406 if (ti_spi_fill_fifo(sc) == -1) in ti_spi_pio_transfer()
408 if (ti_spi_drain_fifo(sc) == -1) in ti_spi_pio_transfer()
433 uint32_t clockhz, cs, mode, reg; in ti_spi_transfer() local
437 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, in ti_spi_transfer()
439 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, in ti_spi_transfer()
443 spibus_get_cs(child, &cs); in ti_spi_transfer()
447 cs &= ~SPIBUS_CS_HIGH; in ti_spi_transfer()
449 if (cs > sc->sc_numcs) { in ti_spi_transfer()
451 cs, device_get_nameunit(child)); in ti_spi_transfer()
465 while (sc->sc_flags & TI_SPI_BUSY) in ti_spi_transfer()
466 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); in ti_spi_transfer()
469 sc->sc_flags = TI_SPI_BUSY; in ti_spi_transfer()
472 sc->sc_cs = cs; in ti_spi_transfer()
473 sc->sc_cmd = cmd; in ti_spi_transfer()
474 sc->sc_read = 0; in ti_spi_transfer()
475 sc->sc_written = 0; in ti_spi_transfer()
476 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; in ti_spi_transfer()
477 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); in ti_spi_transfer()
478 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) in ti_spi_transfer()
479 sc->sc_fifolvl = 1; /* FIFO disabled. */ in ti_spi_transfer()
481 sc->sc_fifolvl = 1; in ti_spi_transfer()
484 ti_spi_set_clock(sc, sc->sc_cs, clockhz); in ti_spi_transfer()
489 /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */ in ti_spi_transfer()
490 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
496 reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */ in ti_spi_transfer()
497 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); in ti_spi_transfer()
507 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); in ti_spi_transfer()
508 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); in ti_spi_transfer()
510 /* Force CS on. */ in ti_spi_transfer()
511 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
512 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); in ti_spi_transfer()
515 if (sc->sc_fifolvl == 1) in ti_spi_transfer()
518 /* Force CS off. */ in ti_spi_transfer()
519 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
521 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); in ti_spi_transfer()
530 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); in ti_spi_transfer()
532 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); in ti_spi_transfer()
535 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); in ti_spi_transfer()
537 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); in ti_spi_transfer()
540 sc->sc_flags = 0; in ti_spi_transfer()