91 	void (*callback)(unsigned int ch, uint32_t ch_status, void *data);
218 	unsigned int ch, j;  in ti_sdma_intr()  local
231 		for (ch = 0; ch < NUM_DMA_CHANNELS; ch++) {  in ti_sdma_intr()
232 			if (intr & (1 << ch)) {  in ti_sdma_intr()
233 				channel = &sc->sc_channel[ch];  in ti_sdma_intr()
236 				csr = ti_sdma_read_4(sc, DMA4_CSR(ch));  in ti_sdma_intr()
239 					              "%d\n", ch);  in ti_sdma_intr()
244 				if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_intr()
246 					              "channel %d\n", j, ch);  in ti_sdma_intr()
254 								  ch);  in ti_sdma_intr()
257 					              "on channel %u\n", ch);  in ti_sdma_intr()
260 					              "on channel %u\n", ch);  in ti_sdma_intr()
263 					              "channel %u\n", ch);  in ti_sdma_intr()
273 				ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);  in ti_sdma_intr()
274 				ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));  in ti_sdma_intr()
278 					channel->callback(ch, csr, channel->callback_data);  in ti_sdma_intr()
290  *	@ch: upon return contains the channel allocated
313 ti_sdma_activate_channel(unsigned int *ch,  in ti_sdma_activate_channel()  argument
314                           void (*callback)(unsigned int ch, uint32_t status, void *data),  in ti_sdma_activate_channel()  argument
326 	if (ch == NULL)  in ti_sdma_activate_channel()
341 			*ch = i;  in ti_sdma_activate_channel()
347 	channel = &sc->sc_channel[*ch];  in ti_sdma_activate_channel()
378 	for (addr = DMA4_CCR(*ch); addr <= DMA4_COLOR(*ch); addr += 4)  in ti_sdma_activate_channel()
388  *	@ch: the channel to deactivate
399 ti_sdma_deactivate_channel(unsigned int ch)  in ti_sdma_deactivate_channel()  argument
412 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_deactivate_channel()
418 	sc->sc_active_channels &= ~(1 << ch);  in ti_sdma_deactivate_channel()
421 	ti_sdma_write_4(sc, DMA4_CICR(ch), 0);  in ti_sdma_deactivate_channel()
424 	ti_sdma_write_4(sc, DMA4_CCR(ch), 0);  in ti_sdma_deactivate_channel()
427 	ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);  in ti_sdma_deactivate_channel()
429 		ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));  in ti_sdma_deactivate_channel()
433 	for (addr = DMA4_CCR(ch); addr <= DMA4_COLOR(ch); addr += 4)  in ti_sdma_deactivate_channel()
443  *	@ch: the channel to disable IRQ's on
454 ti_sdma_disable_channel_irq(unsigned int ch)  in ti_sdma_disable_channel_irq()  argument
466 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_disable_channel_irq()
472 	sc->sc_channel[ch].reg_cicr = 0x0000;  in ti_sdma_disable_channel_irq()
473 	ti_sdma_write_4(sc, DMA4_CICR(ch), 0x0000);  in ti_sdma_disable_channel_irq()
478 		irq_enable &= ~(1 << ch);  in ti_sdma_disable_channel_irq()
484 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_disable_channel_irq()
493  *	@ch: the channel to enable IRQ's on
513 ti_sdma_enable_channel_irq(unsigned int ch, uint32_t flags)  in ti_sdma_enable_channel_irq()  argument
524 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_enable_channel_irq()
533 	sc->sc_channel[ch].reg_cicr = flags;  in ti_sdma_enable_channel_irq()
536 	ti_sdma_write_4(sc, DMA4_CICR(ch), flags);  in ti_sdma_enable_channel_irq()
540 	irq_enable |= (1 << ch);  in ti_sdma_enable_channel_irq()
545 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_enable_channel_irq()
554  *	@ch: the channel number to get the status of
579 ti_sdma_get_channel_status(unsigned int ch, uint32_t *status)  in ti_sdma_get_channel_status()  argument
590 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_get_channel_status()
597 	csr = ti_sdma_read_4(sc, DMA4_CSR(ch));  in ti_sdma_get_channel_status()
607  *	@ch: the channel number to set the endianness of
622 ti_sdma_start_xfer(unsigned int ch, unsigned int src_paddr,  in ti_sdma_start_xfer()  argument
636 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_start_xfer()
641 	channel = &sc->sc_channel[ch];  in ti_sdma_start_xfer()
644 	ti_sdma_write_4(sc, DMA4_CSDP(ch),  in ti_sdma_start_xfer()
648 	ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);  in ti_sdma_start_xfer()
651 	ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);  in ti_sdma_start_xfer()
654 	ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);  in ti_sdma_start_xfer()
655 	ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);  in ti_sdma_start_xfer()
658 	ti_sdma_write_4(sc, DMA4_CCR(ch), channel->reg_ccr);  in ti_sdma_start_xfer()
661 	ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);  in ti_sdma_start_xfer()
664 	ti_sdma_write_4(sc, DMA4_CSF(ch), 0x0001);  in ti_sdma_start_xfer()
667 	ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);  in ti_sdma_start_xfer()
670 	ti_sdma_write_4(sc, DMA4_CDF(ch), 0x0001);  in ti_sdma_start_xfer()
673 	ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);  in ti_sdma_start_xfer()
676 	ccr = ti_sdma_read_4(sc, DMA4_CCR(ch));  in ti_sdma_start_xfer()
678 	ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);  in ti_sdma_start_xfer()
690  *	@ch: the channel number to use for the transfer
716 ti_sdma_start_xfer_packet(unsigned int ch, unsigned int src_paddr,  in ti_sdma_start_xfer_packet()  argument
730 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_start_xfer_packet()
735 	channel = &sc->sc_channel[ch];  in ti_sdma_start_xfer_packet()
739 		ti_sdma_write_4(sc, DMA4_CSDP(ch),  in ti_sdma_start_xfer_packet()
743 	ti_sdma_write_4(sc, DMA4_CEN(ch), elmcnt);  in ti_sdma_start_xfer_packet()
746 	ti_sdma_write_4(sc, DMA4_CFN(ch), frmcnt);  in ti_sdma_start_xfer_packet()
749 	ti_sdma_write_4(sc, DMA4_CSSA(ch), src_paddr);  in ti_sdma_start_xfer_packet()
750 	ti_sdma_write_4(sc, DMA4_CDSA(ch), dst_paddr);  in ti_sdma_start_xfer_packet()
753 	ti_sdma_write_4(sc, DMA4_CCR(ch),  in ti_sdma_start_xfer_packet()
757 	ti_sdma_write_4(sc, DMA4_CSE(ch), 0x0001);  in ti_sdma_start_xfer_packet()
761 		ti_sdma_write_4(sc, DMA4_CSF(ch), pktsize);  in ti_sdma_start_xfer_packet()
763 		ti_sdma_write_4(sc, DMA4_CDF(ch), pktsize);  in ti_sdma_start_xfer_packet()
766 	ti_sdma_write_4(sc, DMA4_CDE(ch), 0x0001);  in ti_sdma_start_xfer_packet()
769 	ti_sdma_write_4(sc, DMA4_CSR(ch), 0x1FFE);  in ti_sdma_start_xfer_packet()
772 	ccr = ti_sdma_read_4(sc, DMA4_CCR(ch));  in ti_sdma_start_xfer_packet()
774 	ti_sdma_write_4(sc, DMA4_CCR(ch), ccr);  in ti_sdma_start_xfer_packet()
786  *	@ch: the channel number to set the endianness of
797 ti_sdma_stop_xfer(unsigned int ch)  in ti_sdma_stop_xfer()  argument
808 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_stop_xfer()
814 	ti_sdma_write_4(sc, DMA4_CICR(ch), 0);  in ti_sdma_stop_xfer()
817 	ti_sdma_write_4(sc, DMA4_CCR(ch), 0);  in ti_sdma_stop_xfer()
820 	ti_sdma_write_4(sc, DMA4_CSR(ch), DMA4_CSR_CLEAR_MASK);  in ti_sdma_stop_xfer()
822 		ti_sdma_write_4(sc, DMA4_IRQSTATUS_L(j), (1 << ch));  in ti_sdma_stop_xfer()
826 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_stop_xfer()
835  *	@ch: the channel number to set the endianness of
847 ti_sdma_set_xfer_endianess(unsigned int ch, unsigned int src, unsigned int dst)  in ti_sdma_set_xfer_endianess()  argument
857 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_set_xfer_endianess()
862 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_ENDIANISM(1);  in ti_sdma_set_xfer_endianess()
863 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_ENDIANISM(src);  in ti_sdma_set_xfer_endianess()
865 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_ENDIANISM(1);  in ti_sdma_set_xfer_endianess()
866 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_ENDIANISM(dst);  in ti_sdma_set_xfer_endianess()
868 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_set_xfer_endianess()
877  *	@ch: the channel number to set the burst settings of
892 ti_sdma_set_xfer_burst(unsigned int ch, unsigned int src, unsigned int dst)  in ti_sdma_set_xfer_burst()  argument
902 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_set_xfer_burst()
907 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_SRC_BURST_MODE(0x3);  in ti_sdma_set_xfer_burst()
908 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_SRC_BURST_MODE(src);  in ti_sdma_set_xfer_burst()
910 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DST_BURST_MODE(0x3);  in ti_sdma_set_xfer_burst()
911 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DST_BURST_MODE(dst);  in ti_sdma_set_xfer_burst()
913 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_set_xfer_burst()
922  *	@ch: the channel number to set the endianness of
934 ti_sdma_set_xfer_data_type(unsigned int ch, unsigned int type)  in ti_sdma_set_xfer_data_type()  argument
944 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_set_xfer_data_type()
949 	sc->sc_channel[ch].reg_csdp &= ~DMA4_CSDP_DATA_TYPE(0x3);  in ti_sdma_set_xfer_data_type()
950 	sc->sc_channel[ch].reg_csdp |= DMA4_CSDP_DATA_TYPE(type);  in ti_sdma_set_xfer_data_type()
952 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_set_xfer_data_type()
972 ti_sdma_set_callback(unsigned int ch,  in ti_sdma_set_callback()  argument
973                       void (*callback)(unsigned int ch, uint32_t status, void *data),  in ti_sdma_set_callback()  argument
984 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_set_callback()
989 	sc->sc_channel[ch].callback = callback;  in ti_sdma_set_callback()
990 	sc->sc_channel[ch].callback_data = data;  in ti_sdma_set_callback()
992 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_set_callback()
1001  *	@ch: the channel number to set the sync on
1017 ti_sdma_sync_params(unsigned int ch, unsigned int trigger, unsigned int mode)  in ti_sdma_sync_params()  argument
1028 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_sync_params()
1033 	ccr = sc->sc_channel[ch].reg_ccr;  in ti_sdma_sync_params()
1053 	sc->sc_channel[ch].reg_ccr = ccr;  in ti_sdma_sync_params()
1055 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_sync_params()
1064  *	@ch: the channel number to set the endianness of
1080 ti_sdma_set_addr_mode(unsigned int ch, unsigned int src_mode,  in ti_sdma_set_addr_mode()  argument
1092 	if ((sc->sc_active_channels & (1 << ch)) == 0) {  in ti_sdma_set_addr_mode()
1097 	ccr = sc->sc_channel[ch].reg_ccr;  in ti_sdma_set_addr_mode()
1105 	sc->sc_channel[ch].reg_ccr = ccr;  in ti_sdma_set_addr_mode()
1107 	sc->sc_channel[ch].need_reg_write = 1;  in ti_sdma_set_addr_mode()