Lines Matching refs:off
133 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) in ti_mmchs_read_4() argument
136 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); in ti_mmchs_read_4()
140 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) in ti_mmchs_write_4() argument
143 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); in ti_mmchs_write_4()
147 RD4(struct ti_sdhci_softc *sc, bus_size_t off) in RD4() argument
150 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); in RD4()
154 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) in WR4() argument
157 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); in WR4()
161 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) in ti_sdhci_read_1() argument
165 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); in ti_sdhci_read_1()
169 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) in ti_sdhci_read_2() argument
187 if (off == SDHCI_CLOCK_CONTROL) { in ti_sdhci_read_2()
202 if (off == SDHCI_TRANSFER_MODE) { in ti_sdhci_read_2()
204 } else if (off == SDHCI_COMMAND_FLAGS) { in ti_sdhci_read_2()
208 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); in ti_sdhci_read_2()
212 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) in ti_sdhci_read_4() argument
217 val32 = RD4(sc, off); in ti_sdhci_read_4()
223 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) in ti_sdhci_read_4()
229 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) in ti_sdhci_read_4()
236 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, in ti_sdhci_read_multi_4() argument
241 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); in ti_sdhci_read_multi_4()
245 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, in ti_sdhci_write_1() argument
253 if (off == SDHCI_HOST_CONTROL) { in ti_sdhci_write_1()
267 val32 = RD4(sc, off & ~3); in ti_sdhci_write_1()
268 val32 &= ~(0xff << (off & 3) * 8); in ti_sdhci_write_1()
269 val32 |= (val << (off & 3) * 8); in ti_sdhci_write_1()
271 WR4(sc, off & ~3, val32); in ti_sdhci_write_1()
275 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, in ti_sdhci_write_2() argument
286 if (off == SDHCI_CLOCK_CONTROL) { in ti_sdhci_write_2()
306 if (off == SDHCI_TRANSFER_MODE) { in ti_sdhci_write_2()
310 } else if (off == SDHCI_COMMAND_FLAGS) { in ti_sdhci_write_2()
317 val32 = RD4(sc, off & ~3); in ti_sdhci_write_2()
318 val32 &= ~(0xffff << (off & 3) * 8); in ti_sdhci_write_2()
319 val32 |= ((val & 0xffff) << (off & 3) * 8); in ti_sdhci_write_2()
320 WR4(sc, off & ~3, val32); in ti_sdhci_write_2()
324 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, in ti_sdhci_write_4() argument
329 WR4(sc, off, val); in ti_sdhci_write_4()
333 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, in ti_sdhci_write_multi_4() argument
338 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); in ti_sdhci_write_multi_4()