1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
87 	int			sc_bus_inuse;
88 	int			sc_buffer_pos;
89 	int			sc_error;
90 	int			sc_fifo_trsh;
91 	int			sc_timeout;
117 /*	{ 3200000,  1, 113, 115,  7, 10}, - HS mode */
138 #define	TI_I2C_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
139 #define	TI_I2C_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
141 	mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev),	\
143 #define	TI_I2C_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx)
144 #define	TI_I2C_ASSERT_LOCKED(_sc)	mtx_assert(&_sc->sc_mtx, MA_OWNED)
145 #define	TI_I2C_ASSERT_UNLOCKED(_sc)	mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
149 	device_printf((_sc)->sc_dev, fmt, ##args)
155  *	ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
164  *	16-bit value read from the register.
170 	return (bus_read_2(sc->sc_mem_res, off));  in ti_i2c_read_2()
174  *	ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
183  *	16-bit value read from the register.
189 	bus_write_2(sc->sc_mem_res, off, val);  in ti_i2c_write_2()
192 static int
195 	int amount, done, i;  in ti_i2c_transfer_intr()
204 		sc->sc_error = ENXIO;  in ti_i2c_transfer_intr()
209 		sc->sc_error = ENXIO;  in ti_i2c_transfer_intr()
214 		/* Register access ready - transaction complete basically. */  in ti_i2c_transfer_intr()
216 		if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {  in ti_i2c_transfer_intr()
218 			    sc->sc_con_reg | I2C_CON_STP);  in ti_i2c_transfer_intr()
226 	if (sc->sc_buffer->flags & IIC_M_RD) {  in ti_i2c_transfer_intr()
230 			 * Receive draining interrupt - last data received.  in ti_i2c_transfer_intr()
231 			 * The set FIFO threshold won't be reached to trigger  in ti_i2c_transfer_intr()
239 			amount = sc->sc_buffer->len - sc->sc_buffer_pos;  in ti_i2c_transfer_intr()
242 			 * Receive data ready interrupt - FIFO has reached the  in ti_i2c_transfer_intr()
243 			 * set threshold.  in ti_i2c_transfer_intr()
247 			amount = min(sc->sc_fifo_trsh,  in ti_i2c_transfer_intr()
248 			    sc->sc_buffer->len - sc->sc_buffer_pos);  in ti_i2c_transfer_intr()
253 			sc->sc_buffer->buf[sc->sc_buffer_pos++] =   in ti_i2c_transfer_intr()
265 			 * Transmit draining interrupt - FIFO level is below  in ti_i2c_transfer_intr()
266 			 * the set threshold and the amount of data still to  in ti_i2c_transfer_intr()
267 			 * be transferred won't reach the set FIFO threshold.  in ti_i2c_transfer_intr()
275 			amount = sc->sc_buffer->len - sc->sc_buffer_pos;  in ti_i2c_transfer_intr()
278 			 * Transmit data ready interrupt - the FIFO level  in ti_i2c_transfer_intr()
279 			 * is below the set threshold.  in ti_i2c_transfer_intr()
283 			amount = min(sc->sc_fifo_trsh,  in ti_i2c_transfer_intr()
284 			    sc->sc_buffer->len - sc->sc_buffer_pos);  in ti_i2c_transfer_intr()
290 			    sc->sc_buffer->buf[sc->sc_buffer_pos++]);  in ti_i2c_transfer_intr()
302  *	ti_i2c_intr - interrupt handler for the I2C module
316 	int done;  in ti_i2c_intr()
338 	if (sc->sc_buffer != NULL)  in ti_i2c_intr()
342 		sc->sc_error = EINVAL;  in ti_i2c_intr()
354  *	ti_i2c_transfer - called to perform the transfer
367 static int
370 	int err, i, repstart, timeout;  in ti_i2c_transfer()
378 	while (sc->sc_bus_inuse == 1)  in ti_i2c_transfer()
379 		mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);  in ti_i2c_transfer()
382 	sc->sc_bus_inuse = 1;  in ti_i2c_transfer()
387 		sc->sc_buffer = &msgs[i];  in ti_i2c_transfer()
388 		sc->sc_buffer_pos = 0;  in ti_i2c_transfer()
389 		sc->sc_error = 0;  in ti_i2c_transfer()
392 		if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||  in ti_i2c_transfer()
393 		    sc->sc_buffer->len == 0) {  in ti_i2c_transfer()
416 		if (sc->sc_buffer->flags & IIC_M_NOSTOP)  in ti_i2c_transfer()
423 		ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);  in ti_i2c_transfer()
430 		reg = sc->sc_con_reg | I2C_CON_STT;  in ti_i2c_transfer()
433 		if ((sc->sc_buffer->flags & IIC_M_RD) == 0)  in ti_i2c_transfer()
438 		err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);  in ti_i2c_transfer()
440 			err = sc->sc_error;  in ti_i2c_transfer()
456 		ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);  in ti_i2c_transfer()
458 	sc->sc_buffer = NULL;  in ti_i2c_transfer()
459 	sc->sc_bus_inuse = 0;  in ti_i2c_transfer()
469 static int
472 	int timeout;  in ti_i2c_reset()
500 	if (sc->sc_iicbus == NULL)  in ti_i2c_reset()
503 		busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);  in ti_i2c_reset()
511 	 * 23.1.4.3 - HS I2C Software Reset  in ti_i2c_reset()
516 	sc->sc_con_reg = 0;  in ti_i2c_reset()
517 	ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);  in ti_i2c_reset()
520 	bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);  in ti_i2c_reset()
541 	ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);  in ti_i2c_reset()
556 	ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);  in ti_i2c_reset()
562 	 *    (see Table 23-8).  in ti_i2c_reset()
564 	scll = clkcfg->scll & I2C_SCLL_MASK;  in ti_i2c_reset()
565 	sclh = clkcfg->sclh & I2C_SCLH_MASK;  in ti_i2c_reset()
572 	 *    Table 23-8).  in ti_i2c_reset()
581 		if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {  in ti_i2c_reset()
582 			scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;  in ti_i2c_reset()
583 			sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;  in ti_i2c_reset()
584 			sc->sc_con_reg |= I2C_CON_OPMODE_HS;  in ti_i2c_reset()
600 	 * Note: For a 10-bit address, set the corresponding expand Own Address  in ti_i2c_reset()
607 	 * 7. Set the TX threshold (in transmitter mode) and the RX threshold  in ti_i2c_reset()
609 	 *    (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX  in ti_i2c_reset()
610 	 *    threshold - 1), where the TX and RX thresholds are greater than  in ti_i2c_reset()
613 	 * The threshold is set to 5 for now.  in ti_i2c_reset()
615 	fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;  in ti_i2c_reset()
623 	 * 23.1.5.1.1.1.2 - Initialize the I2C Controller  in ti_i2c_reset()
635 	sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;  in ti_i2c_reset()
636 	ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);  in ti_i2c_reset()
669 static int
673 	int err;  in ti_i2c_iicbus_reset()
685 static int
688 	int err;  in ti_i2c_activate()
705  *	ti_i2c_deactivate - deactivates the controller and releases resources
721 	/* Disable the controller - cancel all transactions. */  in ti_i2c_deactivate()
727 	if (sc->sc_irq_h != NULL) {  in ti_i2c_deactivate()
728 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);  in ti_i2c_deactivate()
729 		sc->sc_irq_h = NULL;  in ti_i2c_deactivate()
733 	if (sc->sc_mem_res != NULL) {  in ti_i2c_deactivate()
734 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);  in ti_i2c_deactivate()
735 		sc->sc_mem_res = NULL;  in ti_i2c_deactivate()
739 	if (sc->sc_irq_res != NULL) {  in ti_i2c_deactivate()
740 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);  in ti_i2c_deactivate()
741 		sc->sc_irq_res = NULL;  in ti_i2c_deactivate()
748 static int
751 	int clk, psc, sclh, scll;  in ti_i2c_sysctl_clk()
758 	psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;  in ti_i2c_sysctl_clk()
761 	scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;  in ti_i2c_sysctl_clk()
762 	sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;  in ti_i2c_sysctl_clk()
770 static int
774 	unsigned int val;  in ti_i2c_sysctl_timeout()
775 	int err;  in ti_i2c_sysctl_timeout()
784 	val = sc->sc_timeout;  in ti_i2c_sysctl_timeout()
789 	if ((err == 0) && (req->newptr != NULL)) {  in ti_i2c_sysctl_timeout()
791 		sc->sc_timeout = val;  in ti_i2c_sysctl_timeout()
798 static int
804 	if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))  in ti_i2c_probe()
811 static int
814 	int err, rid;  in ti_i2c_attach()
821 	sc->sc_dev = dev;  in ti_i2c_attach()
825 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,  in ti_i2c_attach()
827 	if (sc->sc_mem_res == NULL) {  in ti_i2c_attach()
834 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,  in ti_i2c_attach()
836 	if (sc->sc_irq_res == NULL) {  in ti_i2c_attach()
837 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);  in ti_i2c_attach()
852 	sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;  in ti_i2c_attach()
860 	    sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);  in ti_i2c_attach()
862 	/* Set the FIFO threshold to 5 for now. */  in ti_i2c_attach()
863 	sc->sc_fifo_trsh = 5;  in ti_i2c_attach()
866 	sc->sc_timeout = 5*hz;  in ti_i2c_attach()
879 	err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,  in ti_i2c_attach()
880 	    NULL, ti_i2c_intr, sc, &sc->sc_irq_h);  in ti_i2c_attach()
885 	if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {  in ti_i2c_attach()
903 static int
907 	int rv;  in ti_i2c_detach()