32  * here uses 0-5.
74 #define	TI_GPIO_REVISION		0x0000
75 #define	TI_GPIO_SYSCONFIG		0x0010
76 #define	TI_GPIO_IRQSTATUS_RAW_0		0x0024
77 #define	TI_GPIO_IRQSTATUS_RAW_1		0x0028
78 #define	TI_GPIO_IRQSTATUS_0		0x002C	/* writing a 0 has no effect */
79 #define	TI_GPIO_IRQSTATUS_1		0x0030	/* writing a 0 has no effect */
80 #define	TI_GPIO_IRQSTATUS_SET_0		0x0034	/* writing a 0 has no effect */
81 #define	TI_GPIO_IRQSTATUS_SET_1		0x0038	/* writing a 0 has no effect */
82 #define	TI_GPIO_IRQSTATUS_CLR_0		0x003C	/* writing a 0 has no effect */
83 #define	TI_GPIO_IRQSTATUS_CLR_1		0x0040	/* writing a 0 has no effect */
84 #define	TI_GPIO_IRQWAKEN_0		0x0044
85 #define	TI_GPIO_IRQWAKEN_1		0x0048
86 #define	TI_GPIO_SYSSTATUS		0x0114
87 #define	TI_GPIO_IRQSTATUS1		0x0118
88 #define	TI_GPIO_IRQENABLE1		0x011C
89 #define	TI_GPIO_WAKEUPENABLE		0x0120
90 #define	TI_GPIO_IRQSTATUS2		0x0128
91 #define	TI_GPIO_IRQENABLE2		0x012C
92 #define	TI_GPIO_CTRL			0x0130
93 #define	TI_GPIO_OE			0x0134
94 #define	TI_GPIO_DATAIN			0x0138
95 #define	TI_GPIO_DATAOUT			0x013C
96 #define	TI_GPIO_LEVELDETECT0		0x0140	/* RW register */
97 #define	TI_GPIO_LEVELDETECT1		0x0144	/* RW register */
98 #define	TI_GPIO_RISINGDETECT		0x0148	/* RW register */
99 #define	TI_GPIO_FALLINGDETECT		0x014C	/* RW register */
100 #define	TI_GPIO_DEBOUNCENABLE		0x0150
101 #define	TI_GPIO_DEBOUNCINGTIME		0x0154
102 #define	TI_GPIO_CLEARWKUPENA		0x0180
103 #define	TI_GPIO_SETWKUENA		0x0184
104 #define	TI_GPIO_CLEARDATAOUT		0x0190
105 #define	TI_GPIO_SETDATAOUT		0x0194
110 #define	OMAP4_GPIO_REV			0x50600801
111 #define	AM335X_FIRST_GPIO_BANK		0
113 #define	AM335X_GPIO_REV			0x50600801
117 #define OMAP4_GPIO1_REV			0x00000
118 #define OMAP4_GPIO2_REV			0x55000
119 #define OMAP4_GPIO3_REV			0x57000
120 #define OMAP4_GPIO4_REV			0x59000
121 #define OMAP4_GPIO5_REV			0x5b000
122 #define OMAP4_GPIO6_REV			0x5d000
124 #define AM335X_GPIO0_REV		0x07000
125 #define AM335X_GPIO1_REV		0x4C000
126 #define AM335X_GPIO2_REV		0xAC000
127 #define AM335X_GPIO3_REV		0xAE000
148 	return (0);  in ti_gpio_rev()
261  *	Returns 0 on success otherwise an error code
269 	return (0);  in ti_gpio_pin_max()
279 	return (0);  in ti_gpio_valid_pin()
303  *	Returns 0 on success otherwise an error code
311 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_getcaps()
319 	return (0);  in ti_gpio_pin_getcaps()
336  *	Returns 0 on success otherwise an error code
344 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_getflags()
352 	return (0);  in ti_gpio_pin_getflags()
368  *	Returns 0 on success otherwise an error code
376 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_getname()
381 	name[GPIOMAXNAME - 1] = '\0';  in ti_gpio_pin_getname()
383 	return (0);  in ti_gpio_pin_getname()
403  *	Returns 0 on success otherwise an error code
412 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_setflags()
417 	if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {  in ti_gpio_pin_setflags()
431 	return (0);  in ti_gpio_pin_setflags()
446  *	Returns 0 on success otherwise a error code
455 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_set()
466 	return (0);  in ti_gpio_pin_set()
482  *	Returns 0 on success otherwise a error code
491 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_get()
505 	*value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;  in ti_gpio_pin_get()
508 	return (0);  in ti_gpio_pin_get()
521  *	Returns 0 on success otherwise a error code
530 	if (ti_gpio_valid_pin(sc, pin) != 0)  in ti_gpio_pin_toggle()
543 	return (0);  in ti_gpio_pin_toggle()
565 				sc->sc_bank = 0;  in ti_gpio_bank_init()
588 				sc->sc_bank = 0;  in ti_gpio_bank_init()
619 		    "of GPIO module (revision:0x%08x)\n", rev);  in ti_gpio_bank_init()
624 	ti_gpio_intr_clr(sc, 0xffffffff);  in ti_gpio_bank_init()
627 	reg_oe = 0xffffffff;  in ti_gpio_bank_init()
628 	reg_set = 0;  in ti_gpio_bank_init()
629 	for (pin = 0; pin < PINS_PER_BANK; pin++) {  in ti_gpio_bank_init()
641 	return (0);  in ti_gpio_bank_init()
655  *	Always returns 0
669 	sc->sc_mem_rid = 0;  in ti_gpio_attach()
678 	sc->sc_irq_rid = 0;  in ti_gpio_attach()
692 	    &sc->sc_irq_hdl) != 0) {  in ti_gpio_attach()
699 	if (ti_gpio_pic_attach(sc) != 0) {  in ti_gpio_attach()
713 		if (err != 0) {  in ti_gpio_attach()
725 	return (0);  in ti_gpio_attach()
739  *	Always returns 0
750 		ti_gpio_intr_clr(sc, 0xffffffff);  in ti_gpio_detach()
768 	return (0);  in ti_gpio_detach()
785 	/* Writing a 0 has no effect. */  in ti_gpio_isrc_mask()
793 	/* Writing a 0 has no effect. */  in ti_gpio_isrc_unmask()
801 	/* Writing a 0 has no effect. */  in ti_gpio_isrc_eoi()
826 	for (irq = 0; irq < sc->sc_maxpin; irq++) {  in ti_gpio_intr()
828 		if ((reg & tgi->tgi_mask) == 0)  in ti_gpio_intr()
832 		if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {  in ti_gpio_intr()
854 	for (irq = 0; irq < sc->sc_maxpin; irq++) {  in ti_gpio_pic_attach()
860 		    sc->sc_dev, 0, "%s,%u", name, irq);  in ti_gpio_pic_attach()
861 		if (error != 0)  in ti_gpio_pic_attach()
868 	return (0);  in ti_gpio_pic_attach()
929 	 *	bits[3:0] trigger type and level flags:  in ti_gpio_pic_map_fdt()
935 	if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin)  in ti_gpio_pic_map_fdt()
952 	*irqp = daf->cells[0];  in ti_gpio_pic_map_fdt()
955 	return (0);  in ti_gpio_pic_map_fdt()
976 	return (0);  in ti_gpio_pic_map_gpio()
1005 	if (error == 0)  in ti_gpio_pic_map_intr()
1054 	if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq)  in ti_gpio_pic_setup_intr()
1061 	if (isrc->isrc_handlers != 0)  in ti_gpio_pic_setup_intr()
1062 		return (tgi->tgi_mode == mode ? 0 : EINVAL);  in ti_gpio_pic_setup_intr()
1065 	return (0);  in ti_gpio_pic_setup_intr()
1075 	if (isrc->isrc_handlers == 0)  in ti_gpio_pic_teardown_intr()
1077 	return (0);  in ti_gpio_pic_teardown_intr()
1116 	{0, 0},