1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
64 #define TI_EDMA3CC_DCHMAP(p)		(0x100 + ((p)*4))
65 #define TI_EDMA3CC_DMAQNUM(n)		(0x240 + ((n)*4))
74 #define TI_EDMA3CC_QRAE(p)		(0x380 + ((p)*4))
90 #define TI_EDMA3CC_DMAQNUM_SET(c,q)	((0x7 & (q)) << (((c) % 8) * 4))
91 #define TI_EDMA3CC_DMAQNUM_CLR(c)	(~(0x7 << (((c) % 8) * 4)))
92 #define TI_EDMA3CC_QDMAQNUM_SET(c,q)	((0x7 & (q)) << ((c) * 4))
93 #define TI_EDMA3CC_QDMAQNUM_CLR(c)	(~(0x7 << ((c) * 4)))
101 	 * We use one-element array in case if we need to add 
113 	{ -1,               0,  0 }
119 	{ -1,               0,  0 }
123 #define ti_edma3_cc_rd_4(reg)		bus_read_4(ti_edma3_sc->mem_res[0], reg)
124 #define ti_edma3_cc_wr_4(reg, val)	bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
165 	sc->sc_dev = dev;  in ti_edma3_attach()
168 	err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res);  in ti_edma3_attach()
175 	err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res);  in ti_edma3_attach()
192 		err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC |  in ti_edma3_attach()
194 		    sc, &sc->ih_cookie[i]);  in ti_edma3_attach()
252 	/* Enable DMA channels 0-63 */  in ti_edma3_init()
269 	ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1);  in ti_edma3_init()
282 ti_edma3_enable_event_intr(unsigned int ch)  in ti_edma3_enable_event_intr()  argument
286 	if (ch >= TI_EDMA3_NUM_DMA_CHS)  in ti_edma3_enable_event_intr()
289 	if (ch < 32) {  in ti_edma3_enable_event_intr()
290 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch);  in ti_edma3_enable_event_intr()
292 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32));  in ti_edma3_enable_event_intr()
299 ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)  in ti_edma3_request_dma_ch()  argument
303 	if (ch >= TI_EDMA3_NUM_DMA_CHS)  in ti_edma3_request_dma_ch()
307 	if (ch < 32) {  in ti_edma3_request_dma_ch()
309 		reg |= (0x01 << ch);  in ti_edma3_request_dma_ch()
313 		reg |= (0x01 << (ch - 32));  in ti_edma3_request_dma_ch()
318 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3));  in ti_edma3_request_dma_ch()
319 	reg &= TI_EDMA3CC_DMAQNUM_CLR(ch);  in ti_edma3_request_dma_ch()
320 	reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn);  in ti_edma3_request_dma_ch()
321 	ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg);  in ti_edma3_request_dma_ch()
324 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));  in ti_edma3_request_dma_ch()
326 	reg |= TI_EDMA3CC_OPT_TCC_SET(ch);  in ti_edma3_request_dma_ch()
327 	ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);  in ti_edma3_request_dma_ch()
333 ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn)  in ti_edma3_request_qdma_ch()  argument
337 	if (ch >= TI_EDMA3_NUM_DMA_CHS)  in ti_edma3_request_qdma_ch()
342 	reg |= (0x01 << ch);  in ti_edma3_request_qdma_ch()
347 	reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn);  in ti_edma3_request_qdma_ch()
351 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));  in ti_edma3_request_qdma_ch()
353 	reg |= TI_EDMA3CC_OPT_TCC_SET(ch);  in ti_edma3_request_qdma_ch()
354 	ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);  in ti_edma3_request_qdma_ch()
360 ti_edma3_enable_transfer_manual(unsigned int ch)  in ti_edma3_enable_transfer_manual()  argument
362 	if (ch >= TI_EDMA3_NUM_DMA_CHS)  in ti_edma3_enable_transfer_manual()
366 	if (ch < 32) {  in ti_edma3_enable_transfer_manual()
367 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 <<  ch);  in ti_edma3_enable_transfer_manual()
369 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 <<  (ch - 32));  in ti_edma3_enable_transfer_manual()
376 ti_edma3_enable_transfer_qdma(unsigned int ch)  in ti_edma3_enable_transfer_qdma()  argument
378 	if (ch >= TI_EDMA3_NUM_QDMA_CHS)  in ti_edma3_enable_transfer_qdma()
382 	ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch));  in ti_edma3_enable_transfer_qdma()
388 ti_edma3_enable_transfer_event(unsigned int ch)  in ti_edma3_enable_transfer_event()  argument
390 	if (ch >= TI_EDMA3_NUM_DMA_CHS)  in ti_edma3_enable_transfer_event()
395 	if(ch < 32) {  in ti_edma3_enable_transfer_event()
396 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch));  in ti_edma3_enable_transfer_event()
397 		ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch));  in ti_edma3_enable_transfer_event()
398 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch));  in ti_edma3_enable_transfer_event()
400 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32));  in ti_edma3_enable_transfer_event()
401 		ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32));  in ti_edma3_enable_transfer_event()
402 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32));  in ti_edma3_enable_transfer_event()
409 ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs)  in ti_edma3_param_write()  argument
411 	bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),  in ti_edma3_param_write()
416 ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs)  in ti_edma3_param_read()  argument
418 	bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),  in ti_edma3_param_read()