63 #define TI_EDMA3CC_PID			0x000
64 #define TI_EDMA3CC_DCHMAP(p)		(0x100 + ((p)*4))
65 #define TI_EDMA3CC_DMAQNUM(n)		(0x240 + ((n)*4))
66 #define TI_EDMA3CC_QDMAQNUM		0x260
67 #define TI_EDMA3CC_EMCR			0x308
68 #define TI_EDMA3CC_EMCRH		0x30C
69 #define TI_EDMA3CC_QEMCR		0x314
70 #define TI_EDMA3CC_CCERR		0x318
71 #define TI_EDMA3CC_CCERRCLR		0x31C
72 #define TI_EDMA3CC_DRAE(p)		(0x340 + ((p)*8))
73 #define TI_EDMA3CC_DRAEH(p)		(0x344 + ((p)*8))
74 #define TI_EDMA3CC_QRAE(p)		(0x380 + ((p)*4))
75 #define TI_EDMA3CC_S_ESR(p)		(0x2010 + ((p)*0x200))
76 #define TI_EDMA3CC_S_ESRH(p)		(0x2014 + ((p)*0x200))
77 #define TI_EDMA3CC_S_SECR(p)		(0x2040 + ((p)*0x200))
78 #define TI_EDMA3CC_S_SECRH(p)		(0x2044 + ((p)*0x200))
79 #define TI_EDMA3CC_S_EESR(p)		(0x2030 + ((p)*0x200))
80 #define TI_EDMA3CC_S_EESRH(p)		(0x2034 + ((p)*0x200))
81 #define TI_EDMA3CC_S_IESR(p)		(0x2060 + ((p)*0x200))
82 #define TI_EDMA3CC_S_IESRH(p)		(0x2064 + ((p)*0x200))
83 #define TI_EDMA3CC_S_IPR(p)		(0x2068 + ((p)*0x200))
84 #define TI_EDMA3CC_S_IPRH(p)		(0x206C + ((p)*0x200))
85 #define TI_EDMA3CC_S_QEESR(p)		(0x208C + ((p)*0x200))
87 #define TI_EDMA3CC_PARAM_OFFSET		0x4000
88 #define TI_EDMA3CC_OPT(p)		(TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20))
90 #define TI_EDMA3CC_DMAQNUM_SET(c,q)	((0x7 & (q)) << (((c) % 8) * 4))
91 #define TI_EDMA3CC_DMAQNUM_CLR(c)	(~(0x7 << (((c) % 8) * 4)))
92 #define TI_EDMA3CC_QDMAQNUM_SET(c,q)	((0x7 & (q)) << ((c) * 4))
93 #define TI_EDMA3CC_QDMAQNUM_CLR(c)	(~(0x7 << ((c) * 4)))
95 #define TI_EDMA3CC_OPT_TCC_CLR		(~(0x3F000))
96 #define TI_EDMA3CC_OPT_TCC_SET(p)	(((0x3F000 >> 12) & (p)) << 12)
112 	{ SYS_RES_MEMORY,   0,  RF_ACTIVE },
113 	{ -1,               0,  0 }
116 	{ SYS_RES_IRQ,      0,  RF_ACTIVE },
119 	{ -1,               0,  0 }
123 #define ti_edma3_cc_rd_4(reg)		bus_read_4(ti_edma3_sc->mem_res[0], reg)
124 #define ti_edma3_cc_wr_4(reg, val)	bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
150 	return (0);  in ti_edma3_probe()
191 	for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) {  in ti_edma3_attach()
202 	return (0);  in ti_edma3_attach()
208 	{0, 0},
217 DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, 0, 0);
245 	ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF);  in ti_edma3_init()
246 	ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF);  in ti_edma3_init()
247 	ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF);  in ti_edma3_init()
250 	ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF);  in ti_edma3_init()
252 	/* Enable DMA channels 0-63 */  in ti_edma3_init()
253 	ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF);  in ti_edma3_init()
254 	ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF);  in ti_edma3_init()
256 	for (i = 0; i < 64; i++) {  in ti_edma3_init()
261 	for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) {  in ti_edma3_init()
269 	ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1);  in ti_edma3_init()
272 	for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) {  in ti_edma3_init()
290 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch);  in ti_edma3_enable_event_intr()
292 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32));  in ti_edma3_enable_event_intr()
294 	return 0;  in ti_edma3_enable_event_intr()
308 		reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0));  in ti_edma3_request_dma_ch()
309 		reg |= (0x01 << ch);  in ti_edma3_request_dma_ch()
310 		ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg);  in ti_edma3_request_dma_ch()
312 		reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0));  in ti_edma3_request_dma_ch()
313 		reg |= (0x01 << (ch - 32));  in ti_edma3_request_dma_ch()
314 		ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg);  in ti_edma3_request_dma_ch()
329 	return 0;  in ti_edma3_request_dma_ch()
341 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0));  in ti_edma3_request_qdma_ch()
342 	reg |= (0x01 << ch);  in ti_edma3_request_qdma_ch()
343 	ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg);  in ti_edma3_request_qdma_ch()
356 	return 0;  in ti_edma3_request_qdma_ch()
367 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 <<  ch);  in ti_edma3_enable_transfer_manual()
369 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 <<  (ch - 32));  in ti_edma3_enable_transfer_manual()
372 	return 0;  in ti_edma3_enable_transfer_manual()
382 	ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch));  in ti_edma3_enable_transfer_qdma()
384 	return 0;  in ti_edma3_enable_transfer_qdma()
396 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch));  in ti_edma3_enable_transfer_event()
398 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch));  in ti_edma3_enable_transfer_event()
400 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32));  in ti_edma3_enable_transfer_event()
402 		ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32));  in ti_edma3_enable_transfer_event()
405 	return 0;  in ti_edma3_enable_transfer_event()
411 	bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),  in ti_edma3_param_write()
418 	bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch),  in ti_edma3_param_read()