153 	ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE);  in ti_adc_disable()
160 	ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS));  in ti_adc_disable()
163 	count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_disable()
165 		(void)ADC_READ4(sc, ADC_FIFO0DATA);  in ti_adc_disable()
166 		count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_disable()
169 	count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_disable()
171 		(void)ADC_READ4(sc, ADC_FIFO1DATA);  in ti_adc_disable()
172 		count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_disable()
198 		if (enabled != ADC_READ4(sc, ADC_STEPENABLE))  in ti_adc_setup()
216 	val = ADC_READ4(sc, reg);  in ti_adc_input_setup()
264 	reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1;  in ti_adc_clockdiv_proc()
338 	reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY;  in ti_adc_open_delay_proc()
396 	count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_read_data()
398 		data = ADC_READ4(sc, ADC_FIFO0DATA);  in ti_adc_read_data()
405 		count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_read_data()
434 	count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_tsc_read_data()
440 		data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK;  in ti_adc_tsc_read_data()
441 		count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK;  in ti_adc_tsc_read_data()
507 	rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW);  in ti_adc_intr()
508 	status = ADC_READ4(sc, ADC_IRQSTATUS);  in ti_adc_intr()
660 	val = ADC_READ4(sc, ADC_IDLECONFIG);  in ti_adc_tsc_init()
845 	rev = ADC_READ4(sc, ti_sysc_get_rev_address_offset_host(device_get_parent(dev)));  in ti_adc_attach()
855 	reg = ADC_READ4(sc, ADC_CTRL);  in ti_adc_attach()