57 	device_t		sc_dev;  member
83 	sc->clkdom = clkdom_create(sc->sc_dev);  in register_clk()
85 		DPRINTF(sc->sc_dev, "Failed to create clkdom\n");  in register_clk()
91 		DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err);  in register_clk()
97 		DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err);  in register_clk()
128 	sc->sc_dev = dev;  in ti_divider_attach()
146 		device_printf(sc->sc_dev, "ti,index-power-of-two - Not implemented\n");  in ti_divider_attach()
155 		device_printf(sc->sc_dev, "clock-output-names\n");  in ti_divider_attach()
157 		device_printf(sc->sc_dev, "ti,dividers\n");  in ti_divider_attach()
159 		device_printf(sc->sc_dev, "ti,min-div - Not implemented\n");  in ti_divider_attach()
162 		device_printf(sc->sc_dev, "ti,autoidle-shift - Not implemented\n");  in ti_divider_attach()
164 		device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n");  in ti_divider_attach()
166 		device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n");  in ti_divider_attach()
174 	DPRINTF(sc->sc_dev, "div_def.i_width %x\n", sc->div_def.i_width);  in ti_divider_attach()
176 	read_clock_cells(sc->sc_dev, &sc->clock_cell);  in ti_divider_attach()
178 	create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);  in ti_divider_attach()
180 	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);  in ti_divider_attach()
184 		DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");  in ti_divider_attach()
185 		bus_attach_children(sc->sc_dev);  in ti_divider_attach()
193 		DPRINTF(sc->sc_dev, "register_clk failed\n");  in ti_divider_attach()
194 		bus_attach_children(sc->sc_dev);  in ti_divider_attach()
202 	bus_attach_children(sc->sc_dev);  in ti_divider_attach()
224 	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef);  in ti_divider_new_pass()
227 		DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n");  in ti_divider_new_pass()
234 		DPRINTF(sc->sc_dev, "new_pass register_clk failed\n");  in ti_divider_new_pass()