Lines Matching +full:0 +full:x46000
32 #define DMT_TIDR 0x00 /* Identification Register */
33 #define DMT_TIOCP_CFG 0x10 /* OCP Configuration Reg */
34 #define DMT_TIOCP_RESET (1 << 0) /* TIOCP perform soft reset */
35 #define DMT_IQR_EOI 0x20 /* IRQ End-Of-Interrupt Reg */
36 #define DMT_IRQSTATUS_RAW 0x24 /* IRQSTATUS Raw Reg */
37 #define DMT_IRQSTATUS 0x28 /* IRQSTATUS Reg */
38 #define DMT_IRQENABLE_SET 0x2c /* IRQSTATUS Set Reg */
39 #define DMT_IRQENABLE_CLR 0x30 /* IRQSTATUS Clear Reg */
40 #define DMT_IRQWAKEEN 0x34 /* IRQ Wakeup Enable Reg */
41 #define DMT_IRQ_MAT (1 << 0) /* IRQ: Match */
45 #define DMT_TCLR 0x38 /* Control Register */
46 #define DMT_TCLR_START (1 << 0) /* Start timer */
53 #define DMT_TCLR_CAPTRAN_NONE (0 << 8) /* Capture: none */
58 #define DMT_TCLR_TRGMODE_NONE (0 << 10) /* Trigger off */
63 #define DMT_TCLR_GPO_CFG (1 << 14) /* Tmr pin conf, 0=out, 1=in */
64 #define DMT_TCRR 0x3C /* Counter Register */
65 #define DMT_TLDR 0x40 /* Load Reg */
66 #define DMT_TTGR 0x44 /* Trigger Reg */
67 #define DMT_TWPS 0x48 /* Write Posted Status Reg */
68 #define DMT_TMAR 0x4C /* Match Reg */
69 #define DMT_TCAR1 0x50 /* Capture Reg */
70 #define DMT_TSICR 0x54 /* Synchr. Interface Ctrl Reg */
72 #define DMT_TCAR2 0x48 /* Capture Reg */
76 #define DMTIMER0_REV 0x05000
77 #define DMTIMER1_1MS_REV 0x31000
79 #define DMTIMER2_REV 0x40000
80 #define DMTIMER3_REV 0x42000
81 #define DMTIMER4_REV 0x44000
82 #define DMTIMER5_REV 0x46000
83 #define DMTIMER6_REV 0x48000
84 #define DMTIMER7_REV 0x4A000