1 /*-
8  * 1. Redistributions of source code must retain the above copyright
28  * AM335x PPS driver using DMTimer capture.
31  * hardware's ability to latch the timer's count register in response to a
32  * signal on an IO pin.  Each of timers 4-7 have an associated pin, and this
39  * latched value from the timer.  The remaining work (done by pps_event() while
40  * holding a mutex) is scheduled to be done later in a non-interrupt context.
67 #include <arm/ti/am335x/am335x_scm_padconf.h>
93 	{"ti,am335x-timer",     1},
94 	{"ti,am335x-timer-1ms", 1},
100  * A table relating pad names to the hardware timer number they can be mux'd to.
127  * This is either brilliantly user-friendly, or utterly lame...
129  * The am335x chip is used on the popular Beaglebone boards.  Those boards have
130  * pins for all four capture-capable timers available on the P8 header. Allow
138 	{"P8-7",  "GPMC_ADVn_ALE"},
139 	{"P8-9",  "GPMC_BEn0_CLE"},
140 	{"P8-10", "GPMC_WEn"},
141 	{"P8-8",  "GPMC_OEn_REn",},
145 #define	DMTIMER_READ4(sc, reg)		bus_read_4((sc)->mem_res, (reg))
146 #define	DMTIMER_WRITE4(sc, reg, val)	bus_write_4((sc)->mem_res, (reg), (val))
149  * Translate a short friendly case-insensitive name to its canonical name.
156 	for (nn = dmtpps_pin_nicks; nn->nick != NULL; nn++)  in dmtpps_translate_nickname()
157 		if (strcasecmp(nick, nn->nick) == 0)  in dmtpps_translate_nickname()
158 			return nn->name;  in dmtpps_translate_nickname()
164  * an error, return 0.  If so, try to configure that pin as a timer capture
165  * input pin, and if that works, then we have our timer unit number and if it
166  * fails that IS an error, return -1.
180 	for (pi = dmtpps_padinfo; pi->ballname != NULL; pi++) {  in dmtpps_find_tmr_num_by_tunable()
181 		if (strcmp(ballname, pi->ballname) != 0)  in dmtpps_find_tmr_num_by_tunable()
183 		snprintf(muxmode, sizeof(muxmode), "timer%d", pi->tmr_num);  in dmtpps_find_tmr_num_by_tunable()
184 		err = ti_pinmux_padconf_set(pi->ballname, muxmode,  in dmtpps_find_tmr_num_by_tunable()
189 			return (-1);  in dmtpps_find_tmr_num_by_tunable()
194 		return (pi->tmr_num);  in dmtpps_find_tmr_num_by_tunable()
199 	return (-1);  in dmtpps_find_tmr_num_by_tunable()
204  * input pin.  If so, return the timer number, if not return 0.
215 	for (pi = dmtpps_padinfo; pi->ballname != NULL; pi++) {  in dmtpps_find_tmr_num_by_padconf()
216 		err = ti_pinmux_padconf_get(pi->ballname, &padmux, &padstate);  in dmtpps_find_tmr_num_by_padconf()
217 		snprintf(muxmode, sizeof(muxmode), "timer%d", pi->tmr_num);  in dmtpps_find_tmr_num_by_padconf()
220 			return (pi->tmr_num);  in dmtpps_find_tmr_num_by_padconf()
227  * Figure out which hardware timer number to use based on input pin
241 		tmr_num = -1; /* Must return non-zero to prevent re-probing. */  in dmtpps_find_tmr_num()
254 		newmode = sc->pps_state.ppsparam.mode & PPS_CAPTUREASSERT;  in dmtpps_set_hw_capture()
256 	if (newmode == sc->pps_curmode)  in dmtpps_set_hw_capture()
258 	sc->pps_curmode = newmode;  in dmtpps_set_hw_capture()
261 		sc->tclr |= DMT_TCLR_CAPTRAN_LOHI;  in dmtpps_set_hw_capture()
263 		sc->tclr &= ~DMT_TCLR_CAPTRAN_MASK;  in dmtpps_set_hw_capture()
264 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);  in dmtpps_set_hw_capture()
272 	sc = tc->tc_priv;  in dmtpps_get_timecount()
282 	sc = tc->tc_priv;  in dmtpps_poll()
293 	 * TCAR status to re-arm the capture for the next second, we have to  in dmtpps_poll()
303 		pps_capture(&sc->pps_state);  in dmtpps_poll()
304 		sc->pps_state.capcount = DMTIMER_READ4(sc, DMT_TCAR1);  in dmtpps_poll()
307 		mtx_lock_spin(&sc->pps_mtx);  in dmtpps_poll()
308 		pps_event(&sc->pps_state, PPS_CAPTUREASSERT);  in dmtpps_poll()
309 		mtx_unlock_spin(&sc->pps_mtx);  in dmtpps_poll()
319 	sc = dev->si_drv1;  in dmtpps_open()
326 	sc->tc.tc_poll_pps = dmtpps_poll;  in dmtpps_open()
338 	sc = dev->si_drv1;  in dmtpps_close()
341 	 * Stop polling and disable capture on last close.  Use the force-off  in dmtpps_close()
344 	sc->tc.tc_poll_pps = NULL;  in dmtpps_close()
357 	sc = dev->si_drv1;  in dmtpps_ioctl()
360 	mtx_lock_spin(&sc->pps_mtx);  in dmtpps_ioctl()
361 	err = pps_ioctl(cmd, data, &sc->pps_state);  in dmtpps_ioctl()
362 	mtx_unlock_spin(&sc->pps_mtx);  in dmtpps_ioctl()
368 	 * mode is now current.  Effectively a no-op if nothing changed.  in dmtpps_ioctl()
392 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in dmtpps_probe()
396 	 * If we haven't chosen which hardware timer to use yet, go do that now.  in dmtpps_probe()
398 	 * hardware timer instance or not.  in dmtpps_probe()
404 	 * Figure out which hardware timer is being probed and see if it matches  in dmtpps_probe()
405 	 * the configured timer number determined earlier.  in dmtpps_probe()
410 			tmr_num = 1;  in dmtpps_probe()
437 	device_set_descf(dev, "AM335x PPS-Capture DMTimer%d", tmr_num);  in dmtpps_probe()
452 	sc->dev = dev;  in dmtpps_attach()
454 	/* Figure out which hardware timer this is and set the name string. */  in dmtpps_attach()
458 			sc->tmr_num = 1;  in dmtpps_attach()
461 			sc->tmr_num = 2;  in dmtpps_attach()
464 			sc->tmr_num = 3;  in dmtpps_attach()
467 			sc->tmr_num = 4;  in dmtpps_attach()
470 			sc->tmr_num = 5;  in dmtpps_attach()
473 			sc->tmr_num = 6;  in dmtpps_attach()
476 			sc->tmr_num = 7;  in dmtpps_attach()
479 	snprintf(sc->tmr_name, sizeof(sc->tmr_name), "DMTimer%d", sc->tmr_num);  in dmtpps_attach()
482 	err = clk_get_by_ofw_index(dev, 0, 0, &sc->clk_fck);  in dmtpps_attach()
495 	err = clk_set_parent_by_clk(sc->clk_fck, sys_clkin);  in dmtpps_attach()
509 	err = clk_get_freq(sc->clk_fck, &sc->sysclk_freq);  in dmtpps_attach()
515 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,  in dmtpps_attach()
516 	    &sc->mem_rid, RF_ACTIVE);  in dmtpps_attach()
517 	if (sc->mem_res == NULL) {  in dmtpps_attach()
522 	 * Configure the timer pulse/capture pin to input/capture mode.  This is  in dmtpps_attach()
526 	sc->tclr = DMT_TCLR_GPO_CFG;  in dmtpps_attach()
527 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);  in dmtpps_attach()
534 	sc->tclr |= DMT_TCLR_START | DMT_TCLR_AUTOLOAD;  in dmtpps_attach()
537 	DMTIMER_WRITE4(sc, DMT_TCLR, sc->tclr);  in dmtpps_attach()
540 	sc->tc.tc_name           = sc->tmr_name;  in dmtpps_attach()
541 	sc->tc.tc_get_timecount  = dmtpps_get_timecount;  in dmtpps_attach()
542 	sc->tc.tc_counter_mask   = ~0u;  in dmtpps_attach()
543 	sc->tc.tc_frequency      = sc->sysclk_freq;  in dmtpps_attach()
544 	sc->tc.tc_quality        = 1000;  in dmtpps_attach()
545 	sc->tc.tc_priv           = sc;  in dmtpps_attach()
547 	tc_init(&sc->tc);  in dmtpps_attach()
556 	 * now, just say we can only capture assert events (the positive-going  in dmtpps_attach()
559 	mtx_init(&sc->pps_mtx, "dmtpps", NULL, MTX_SPIN);  in dmtpps_attach()
560 	sc->pps_state.flags = PPSFLAG_MTX_SPIN;  in dmtpps_attach()
561 	sc->pps_state.ppscap = PPS_CAPTUREASSERT;  in dmtpps_attach()
562 	sc->pps_state.driver_abi = PPS_ABI_VERSION;  in dmtpps_attach()
563 	sc->pps_state.driver_mtx = &sc->pps_mtx;  in dmtpps_attach()
564 	pps_init_abi(&sc->pps_state);  in dmtpps_attach()
576 	if ((err = make_dev_s(&mda, &sc->pps_cdev, PPS_CDEV_NAME)) != 0) {  in dmtpps_attach()
582 		device_printf(sc->dev, "Using %s for PPS device /dev/%s\n",  in dmtpps_attach()
583 		    sc->tmr_name, PPS_CDEV_NAME);  in dmtpps_attach()
614 MODULE_DEPEND(am335x_dmtpps, ti_sysc, 1, 1, 1);