75 #define	T_XUSB_CFG_0				0x000
76 #define	T_XUSB_CFG_1				0x004
79 #define	 CFG_1_IO_SPACE					(1 << 0)
81 #define	T_XUSB_CFG_2				0x008
82 #define	T_XUSB_CFG_3				0x00C
83 #define	T_XUSB_CFG_4				0x010
84 #define	 CFG_4_BASE_ADDRESS(x)				(((x) & 0x1FFFF) << 15)
86 #define	T_XUSB_CFG_5				0x014
87 #define	T_XUSB_CFG_ARU_MAILBOX_CMD		0x0E4
94 #define	T_XUSB_CFG_ARU_MAILBOX_DATA_IN		0x0E8
95 #define	 ARU_MAILBOX_DATA_IN_DATA(x)			(((x) & 0xFFFFFF) <<  0)
96 #define	 ARU_MAILBOX_DATA_IN_TYPE(x)			(((x) & 0x0000FF) << 24)
98 #define	T_XUSB_CFG_ARU_MAILBOX_DATA_OUT		0x0EC
99 #define	 ARU_MAILBOX_DATA_OUT_DATA(x)			(((x) >>  0) & 0xFFFFFF)
100 #define	 ARU_MAILBOX_DATA_OUT_TYPE(x)			(((x) >> 24) & 0x0000FF)
102 #define	T_XUSB_CFG_ARU_MAILBOX_OWNER		0x0F0
105 #define	 ARU_MAILBOX_OWNER_NONE				0
107 #define	XUSB_CFG_ARU_C11_CSBRANGE		0x41C	/* ! UNDOCUMENTED ! */
109 #define	 ARU_C11_CSBRANGE_ADDR(x)			(0x800 + ((x) & 0x1FF))
110 #define	XUSB_CFG_ARU_SMI_INTR			0x428	/* ! UNDOCUMENTED ! */
113 #define	XUSB_CFG_ARU_RST			0x42C	/* ! UNDOCUMENTED ! */
114 #define	 ARU_RST_RESET					(1 << 0)
116 #define	XUSB_HOST_CONFIGURATION			0x180
133 #define	 CONFIGURATION_EN_FPCI				(1 <<  0)
136 #define	XUSB_HOST_FPCI_ERROR_MASKS		0x184
139 #define	 FPCI_ERROR_TARGET_ABORT			(1 <<  0)
141 #define	XUSB_HOST_INTR_MASK			0x188
144 #define	 INTR_INT_MASK					(1 <<  0)
146 #define	XUSB_HOST_CLKGATE_HYSTERESIS		0x1BC
149 #define	XUSB_FALCON_CPUCTL			0x100
155 #define	 CPUCTL_IINVAL					(1 << 0)
157 #define	XUSB_FALCON_BOOTVEC			0x104
158 #define	XUSB_FALCON_DMACTL			0x10C
159 #define	XUSB_FALCON_IMFILLRNG1			0x154
160 #define	 IMFILLRNG1_TAG_HI(x)				(((x) & 0xFFF) << 16)
161 #define	 IMFILLRNG1_TAG_LO(x)				(((x) & 0xFFF) <<  0)
162 #define	XUSB_FALCON_IMFILLCTL			0x158
165 #define	XUSB_CSB_MEMPOOL_APMAP			0x10181C
168 #define	XUSB_CSB_MEMPOOL_ILOAD_ATTR		0x101A00
169 #define	XUSB_CSB_MEMPOOL_ILOAD_BASE_LO		0x101A04
170 #define	XUSB_CSB_MEMPOOL_ILOAD_BASE_HI		0x101A08
171 #define	XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE		0x101A10
172 #define	 L2IMEMOP_SIZE_OFFSET(x)			(((x) & 0x3FF) <<  8)
173 #define	 L2IMEMOP_SIZE_SIZE(x)				(((x) & 0x0FF) << 24)
175 #define	XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG		0x101A14
176 #define	 L2IMEMOP_INVALIDATE_ALL			(0x40 << 24)
177 #define	 L2IMEMOP_LOAD_LOCKED_RESULT			(0x11 << 24)
179 #define	XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT        0x101A18
208 #define	MBOX_CMD_ACK				(0x80 + 0)
209 #define	MBOX_CMD_NAK				(0x80 + 1)
219     mtx_sleep(sc, &sc->mtx, 0, "tegra_xhci", timeout);
314 	"usb2-0",
317 	"usb3-0",
341 	"usb2-0",
345 	"usb3-0",
361 	{NULL,		 	 0}
387 	for (i = 0; sc->soc->regulator_names[i] != NULL; i++) {  in get_fdt_resources()
393 		rv = regulator_get_by_ofw_property(sc->dev, 0,  in get_fdt_resources()
395 		if (rv != 0) {  in get_fdt_resources()
403 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_host",  in get_fdt_resources()
405 	if (rv != 0) {  in get_fdt_resources()
409 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "xusb_ss",  in get_fdt_resources()
411 	if (rv != 0) {  in get_fdt_resources()
417 	for (i = 0; sc->soc->phy_names[i] != NULL; i++) {  in get_fdt_resources()
423 		rv = phy_get_by_ofw_name(sc->dev, 0, sc->soc->phy_names[i],  in get_fdt_resources()
425 		if (rv != 0 && rv != ENOENT) {  in get_fdt_resources()
432 	rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_host",  in get_fdt_resources()
434 	if (rv != 0) {  in get_fdt_resources()
438 	rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_falcon_src",  in get_fdt_resources()
440 	if (rv != 0) {  in get_fdt_resources()
444 	rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_ss",  in get_fdt_resources()
446 	if (rv != 0) {  in get_fdt_resources()
450 	rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_hs_src",  in get_fdt_resources()
452 	if (rv != 0) {  in get_fdt_resources()
456 	rv = clk_get_by_ofw_name(sc->dev, 0, "xusb_fs_src",  in get_fdt_resources()
458 	if (rv != 0) {  in get_fdt_resources()
464 	if (rv != 0) {  in get_fdt_resources()
468 	return (0);  in get_fdt_resources()
477 	if (rv != 0) {  in enable_fdt_resources()
482 	if (rv != 0) {  in enable_fdt_resources()
488 	for (i = 0; i < nitems(sc->regulators); i++) {  in enable_fdt_resources()
492 		if (rv != 0) {  in enable_fdt_resources()
502 	if (rv != 0) {  in enable_fdt_resources()
507 	if (rv != 0) {  in enable_fdt_resources()
513 	clk_set_freq(sc->clk_xusb_ss, TEGRA_XHCI_SS_HIGH_SPEED, 0);  in enable_fdt_resources()
514 	if (rv != 0)  in enable_fdt_resources()
519 	if (rv != 0) {  in enable_fdt_resources()
528 	if (rv != 0) {  in enable_fdt_resources()
534 	if (rv != 0) {  in enable_fdt_resources()
541 	if (rv != 0) {  in enable_fdt_resources()
547 	if (rv != 0) {  in enable_fdt_resources()
553 	if (rv != 0) {  in enable_fdt_resources()
560 	for (i = 0; i < nitems(sc->phys); i++) {  in enable_fdt_resources()
564 		if (rv != 0) {  in enable_fdt_resources()
571 	return (0);  in enable_fdt_resources()
598 		    "CPU mailbox is busy: 0x%08X\n", reg);  in mbox_send_cmd()
606 		    "Cannot acquire CPU mailbox: 0x%08X\n", reg);  in mbox_send_cmd()
616 	for (i = 250; i > 0; i--) {  in mbox_send_cmd()
622 	if (i <= 0) {  in mbox_send_cmd()
624 		    "Command response timeout: 0x%08X\n", reg);  in mbox_send_cmd()
628 	return(0);  in mbox_send_cmd()
644 		    0);  in process_msg()
645 		if (rv == 0) {  in process_msg()
649 		*resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK;  in process_msg()
655 		    0);  in process_msg()
656 		if (rv == 0) {  in process_msg()
660 		*resp_cmd = rv == 0 ? MBOX_CMD_ACK: MBOX_CMD_NAK;  in process_msg()
665 		*resp_cmd = 0;  in process_msg()
697 		*resp_cmd = 0;  in process_msg()
719 		    "XUSB CPU firmware hang!!! CPUCTL: 0x%08X\n",  in intr_mbox()
724 	resp_cmd = 0;  in intr_mbox()
727 	if (resp_cmd != 0)  in intr_mbox()
757 	if (CSB_RD4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO) != 0) {  in load_fw()
759 		    "XUSB CPU is already loaded, CPUCTL: 0x%08X\n",  in load_fw()
761 		return (0);  in load_fw()
774 	fw_vaddr = kmem_alloc_contig(fw_size, M_WAITOK, 0, -1UL, PAGE_SIZE, 0,  in load_fw()
787 	CSB_WR4(sc, XUSB_CSB_MEMPOOL_ILOAD_BASE_LO, fw_base & 0xFFFFFFFF);  in load_fw()
812 	CSB_WR4(sc, XUSB_FALCON_DMACTL, 0);  in load_fw()
814 	for (i = 500; i > 0; i--) {  in load_fw()
820 	if (i <= 0) {  in load_fw()
822 		    "state: 0x%08X\n",  in load_fw()
832 	for (i = 50; i > 0; i--) {  in load_fw()
837 	if (i <= 0) {  in load_fw()
839 		    "state: 0x%08X\n", CSB_RD4(sc, XUSB_FALCON_CPUCTL));  in load_fw()
844 	fw_timespec.tv_nsec = 0;  in load_fw()
849 	    (fw_hdr->version_id >> 24) & 0xFF,(fw_hdr->version_id >> 15) & 0xFF,  in load_fw()
850 	    fw_hdr->version_id & 0xFFFF,  in load_fw()
854 	return (0);  in load_fw()
874 	reg &= ~CFG_4_BASE_ADDRESS(~0);  in init_hw()
895 	if (rv != 0)  in init_hw()
897 	return (0);  in init_hw()
907 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {  in tegra_xhci_probe()
926 	if (error != 0)  in tegra_xhci_detach()
955 	return (0);  in tegra_xhci_detach()
975 	if (rv != 0) {  in tegra_xhci_attach()
980 	if (rv != 0) {  in tegra_xhci_attach()
986 	rid = 0;  in tegra_xhci_attach()
1014 	rid = 0;  in tegra_xhci_attach()
1032 	if (rv != 0) {  in tegra_xhci_attach()
1038 	rv = mbox_send_cmd(sc, MBOX_CMD_MSG_ENABLED, 0);  in tegra_xhci_attach()
1039 	if (rv != 0) {  in tegra_xhci_attach()
1065 	if (rv != 0) {  in tegra_xhci_attach()
1071 	if (rv != 0) {  in tegra_xhci_attach()
1079 	if (rv != 0) {  in tegra_xhci_attach()
1087 	if (rv != 0) {  in tegra_xhci_attach()
1095 	if (rv != 0) {  in tegra_xhci_attach()
1100 	return (0);  in tegra_xhci_attach()