52 #define	CTRL_ICUSB_CTRL			0x15c
55 #define	CTRL_USB_USBMODE		0x1f8
56 #define	  USB_USBMODE_MASK			(3 << 0)
57 #define	  USB_USBMODE_HOST			(3 << 0)
58 #define	  USB_USBMODE_DEVICE			(2 << 0)
60 #define	CTRL_USB_HOSTPC1_DEVLC		0x1b4
61 #define	 USB_HOSTPC1_DEVLC_PTS(x)		(((x) & 0x7) << 29)
65 #define	IF_USB_SUSP_CTRL		0x400
68 #define	 USB_WAKEUP_DEBOUNCE_COUNT(x)		(((x) & 0x7) << 16)
82 #define	 USB_WAKEUP_INT_STS			(1 << 0)
84 #define	IF_USB_PHY_VBUS_SENSORS		0x404
88 #define	UTMIP_XCVR_CFG0			0x808
89 #define	 UTMIP_XCVR_HSSLEW_MSB(x)		((((x) & 0x1fc) >> 2) << 25)
90 #define	 UTMIP_XCVR_SETUP_MSB(x)		((((x) & 0x70) >> 4) << 22)
101 #define	 UTMIP_XCVR_LSFSLEW(x)			(((x) & 0x3) << 10)
102 #define	 UTMIP_XCVR_LSRSLEW(x)			(((x) & 0x3) << 8)
103 #define	 UTMIP_XCVR_FSSLEW(x)			(((x) & 0x3) << 6)
104 #define	 UTMIP_XCVR_HSSLEW(x)			(((x) & 0x3) << 4)
105 #define	 UTMIP_XCVR_SETUP(x)			(((x) & 0xf) << 0)
107 #define	UTMIP_BIAS_CFG0			0x80C
114 #define	 UTMIP_HSDISCON_LEVEL_MSB(x)		((((x) & 0x4) >> 2) << 24)
121 #define	 UTMIP_ACTIVE_TERM_OFFSET(x)		(((x) & 0x7) << 15)
122 #define	 UTMIP_ACTIVE_PULLUP_OFFSET(x)		(((x) & 0x7) << 12)
125 #define	 UTMIP_VBUS_LEVEL_LEVEL(x)		(((x) & 0x3) << 8)
126 #define	 UTMIP_SESS_LEVEL_LEVEL(x)		(((x) & 0x3) << 6)
127 #define	 UTMIP_HSCHIRP_LEVEL(x)			(((x) & 0x3) << 4)
128 #define	 UTMIP_HSDISCON_LEVEL(x)		(((x) & 0x3) << 2)
129 #define	 UTMIP_HSSQUELCH_LEVEL(x)		(((x) & 0x3) << 0)
131 #define	UTMIP_HSRX_CFG0			0x810
132 #define	 UTMIP_KEEP_PATT_ON_ACTIVE(x)		(((x) & 0x3) << 30)
135 #define	 UTMIP_PCOUNT_UPDN_DIV(x)		(((x) & 0xf) << 24)
136 #define	 UTMIP_SQUELCH_EOP_DLY(x)		(((x) & 0x7) << 21)
138 #define	 UTMIP_IDLE_WAIT(x)			(((x) & 0x1f) << 15)
139 #define	 UTMIP_ELASTIC_LIMIT(x)			(((x) & 0x1f) << 10)
144 #define	 UTMIP_PCOUNT_INERTIA(x)		(((x) & 0x3) << 4)
145 #define	 UTMIP_PHASE_ADJUST(x)			(((x) & 0x3) << 2)
147 #define	 UTMIP_USE4SYNC_TRAN			(1 << 0)
149 #define	UTMIP_HSRX_CFG1			0x814
150 #define	 UTMIP_HS_SYNC_START_DLY(x)		(((x) & 0x1F) << 1)
151 #define	 UTMIP_HS_ALLOW_KEEP_ALIVE		(1 << 0)
153 #define	UTMIP_TX_CFG0			0x820
159 #define	 UTMIP_HS_TX_IPG_DLY(x)			(((x) & 0x1f) << 10)
169 #define	 UTMIP_NO_SYNC_NO_EOP			(1 << 0)
171 #define	UTMIP_MISC_CFG0			0x824
172 #define	 UTMIP_DPDM_OBSERVE_SEL(x)		(((x) & 0xf) << 27)
179 #define	 UTMIP_INJECT_ERROR_TYPE(x)		(((x) & 0x3) << 19)
191 #define	 UTMIP_STABLE_COUNT(x)			(((x) & 0x7) << 5)
196 #define	 UTMIP_COMB_TERMS			(1 << 0)
198 #define	UTMIP_MISC_CFG1			0x828
201 #define	UTMIP_DEBOUNCE_CFG0		0x82C
202 #define	 UTMIP_BIAS_DEBOUNCE_B(x)		(((x) & 0xffff) << 16)
203 #define	 UTMIP_BIAS_DEBOUNCE_A(x)		(((x) & 0xffff) << 0)
205 #define	UTMIP_BAT_CHRG_CFG0		0x830
206 #define	 UTMIP_CHRG_DEBOUNCE_TIMESCALE(x) 	(((x) & 0x1f) << 8)
212 #define	 UTMIP_PD_CHRG				(1 << 0)
214 #define	UTMIP_SPARE_CFG0		0x834
222 #define	 HS_RX_IPG_ERROR_ENABLE 		(1 << 0)
224 #define	UTMIP_XCVR_CFG1			0x838
225 #define	 UTMIP_XCVR_RPU_RANGE_ADJ(x)		(((x) & 0x3) << 26)
226 #define	 UTMIP_XCVR_HS_IREF_CAP(x)		(((x) & 0x3) << 24)
227 #define	 UTMIP_XCVR_SPARE(x)			(((x) & 0x3) << 22)
228 #define	 UTMIP_XCVR_TERM_RANGE_ADJ(x)		(((x) & 0xf) << 18)
230 #define	 UTMIP_RCTRL_SW_VAL(x)			(((x) & 0x1f) << 12)
232 #define	 UTMIP_TCTRL_SW_VAL(x)			(((x) & 0x1f) << 6)
238 #define	 UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
240 #define	UTMIP_BIAS_CFG1			0x83c
241 #define	 UTMIP_BIAS_DEBOUNCE_TIMESCALE(x)	(((x) & 0x3f) << 8)
242 #define	 UTMIP_BIAS_PDTRK_COUNT(x)		(((x) & 0x1f) << 3)
245 #define	 UTMIP_FORCE_PDTRK_POWERDOWN		(1 << 0)
250 	USB_IFC_TYPE_UNKNOWN = 0,
256 	USB_DR_MODE_UNKNOWN = 0,
293 	{NULL,				0},
304     0, phynode_class);
317 	for (i = 0; i < 1000; i++) {  in reg_wait()
319 			return (0);  in reg_wait()
339 	    enable ? USB_PHY_CLK_VALID: 0);  in usbphy_utmi_phy_clk()
340 	if (rv != 0) {  in usbphy_utmi_phy_clk()
344 	return (0);  in usbphy_utmi_phy_clk()
363 	val &= ~UTMIP_IDLE_WAIT(~0);  in usbphy_utmi_enable()
364 	val &= ~UTMIP_ELASTIC_LIMIT(~0);  in usbphy_utmi_enable()
370 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);  in usbphy_utmi_enable()
375 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);  in usbphy_utmi_enable()
376 	val |= UTMIP_BIAS_DEBOUNCE_A(0x7530);  /* For 12MHz */  in usbphy_utmi_enable()
401 		if (rv != 0) {  in usbphy_utmi_enable()
407 		if (rv != 0) {  in usbphy_utmi_enable()
416 		val &= ~UTMIP_HSSQUELCH_LEVEL(~0);  in usbphy_utmi_enable()
417 		val &= ~UTMIP_HSDISCON_LEVEL(~0);  in usbphy_utmi_enable()
418 		val &= ~UTMIP_HSDISCON_LEVEL_MSB(~0);  in usbphy_utmi_enable()
425 		if (rv != 0) {  in usbphy_utmi_enable()
437 	val &= ~UTMIP_XCVR_LSFSLEW(~0);  in usbphy_utmi_enable()
438 	val &= ~UTMIP_XCVR_LSRSLEW(~0);  in usbphy_utmi_enable()
439 	val &= ~UTMIP_XCVR_HSSLEW(~0);  in usbphy_utmi_enable()
440 	val &= ~UTMIP_XCVR_HSSLEW_MSB(~0);  in usbphy_utmi_enable()
446 		val &= ~UTMIP_XCVR_SETUP(~0);  in usbphy_utmi_enable()
447 		val &= ~UTMIP_XCVR_SETUP_MSB(~0);  in usbphy_utmi_enable()
457 	val &= ~UTMIP_XCVR_TERM_RANGE_ADJ(~0);  in usbphy_utmi_enable()
462 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);  in usbphy_utmi_enable()
463 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);  in usbphy_utmi_enable()
492 	val &= ~USB_HOSTPC1_DEVLC_PTS(~0);  in usbphy_utmi_enable()
493 	val |= USB_HOSTPC1_DEVLC_PTS(0);  in usbphy_utmi_enable()
496 	return (0);  in usbphy_utmi_enable()
509 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);  in usbphy_utmi_disable()
536 	if (usbpby_enable_cnt <= 0) {  in usbphy_utmi_disable()
538 		if (rv != 0) {  in usbphy_utmi_disable()
549 		if (rv != 0) {  in usbphy_utmi_disable()
555 	return (0);  in usbphy_utmi_disable()
563 	int rv = 0;  in usbphy_phy_enable()
589 	if (rv <= 0)  in usb_get_ifc_mode()
593 	if (strcmp(tmpstr, "utmi") == 0)  in usb_get_ifc_mode()
595 	else if (strcmp(tmpstr, "ulpi") == 0)  in usb_get_ifc_mode()
611 	if (rv <= 0)  in usb_get_dr_mode()
615 	if (strcmp(tmpstr, "device") == 0)  in usb_get_dr_mode()
617 	else if (strcmp(tmpstr, "host") == 0)  in usb_get_dr_mode()
619 	else if (strcmp(tmpstr, "otg") == 0)  in usb_get_dr_mode()
634 	if (rv <= 0)  in usbphy_utmi_read_params()
639 	if (rv <= 0)  in usbphy_utmi_read_params()
644 	if (rv <= 0)  in usbphy_utmi_read_params()
649 	if (rv <= 0)  in usbphy_utmi_read_params()
654 	if (rv <= 0)  in usbphy_utmi_read_params()
659 	if (rv <= 0)  in usbphy_utmi_read_params()
664 	if (rv <= 0)  in usbphy_utmi_read_params()
669 	if (rv <= 0)  in usbphy_utmi_read_params()
674 	if (rv <= 0)  in usbphy_utmi_read_params()
683 		if (rv <= 0)  in usbphy_utmi_read_params()
687 	return (0);  in usbphy_utmi_read_params()
716 	rid = 0;  in usbphy_attach()
734 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "usb", &sc->reset_usb);  in usbphy_attach()
735 	if (rv != 0) {  in usbphy_attach()
739 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->reset_pads);  in usbphy_attach()
740 	if (rv != 0) {  in usbphy_attach()
745 	rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);  in usbphy_attach()
746 	if (rv != 0) {  in usbphy_attach()
750 	rv = clk_get_by_ofw_name(sc->dev, 0, "pll_u", &sc->clk_pllu);  in usbphy_attach()
751 	if (rv != 0) {  in usbphy_attach()
755 	rv = clk_get_by_ofw_name(sc->dev, 0, "utmi-pads", &sc->clk_pads);  in usbphy_attach()
756 	if (rv != 0) {  in usbphy_attach()
762 	if (rv != 0) {  in usbphy_attach()
768 	if (rv != 0) {  in usbphy_attach()
773 	if (rv != 0) {  in usbphy_attach()
792 	if (rv < 0)  in usbphy_attach()
796 		rv = regulator_get_by_ofw_property(sc->dev, 0, "vbus-supply",  in usbphy_attach()
798 		if (rv != 0) {  in usbphy_attach()
804 		if (rv != 0) {  in usbphy_attach()
825 	return (0);  in usbphy_attach()