Lines Matching +full:dvddio +full:- +full:pex +full:- +full:supply
1 /*-
29 * Nvidia Integrated PCI/PCI-Express controller driver.
232 #define PADS_WR4(_sc, _r, _v) bus_write_4((_sc)->pads_mem_res, (_r), (_v))
233 #define PADS_RD4(_sc, _r) bus_read_4((_sc)->pads_mem_res, (_r))
234 #define AFI_WR4(_sc, _r, _v) bus_write_4((_sc)->afi_mem_res, (_r), (_v))
235 #define AFI_RD4(_sc, _r) bus_read_4((_sc)->afi_mem_res, (_r))
265 "avddio-pex-supply",
266 "dvddio-pex-supply",
267 "avdd-pex-pll-supply",
268 "hvdd-pex-supply",
269 "hvdd-pex-pll-e-supply",
270 "vddio-pex-ctl-supply",
271 "avdd-pll-erefe-supply",
284 "avdd-pll-uerefe-supply",
285 "hvddio-pex-supply",
286 "dvddio-pex-supply",
287 "dvdd-pex-pll-supply",
288 "hvdd-pex-pll-e-supply",
289 "vddio-pex-ctl-supply",
302 {"nvidia,tegra124-pcie", (uintptr_t)&tegra124_soc},
303 {"nvidia,tegra210-pcie", (uintptr_t)&tegra210_soc},
379 irq = intr_map_clone_irq(rman_get_start(sc->irq_res)); in tegra_pcib_route_interrupt()
394 offs = sc->cfg_base_addr; in tegra_pcbib_map_cfg()
397 if ((sc->cfg_handle != 0) && (sc->cfg_cur_offs == offs)) in tegra_pcbib_map_cfg()
399 if (sc->cfg_handle != 0) in tegra_pcbib_map_cfg()
400 bus_space_unmap(sc->bus_tag, sc->cfg_handle, 0x800); in tegra_pcbib_map_cfg()
407 rv = bus_space_map(sc->bus_tag, offs, 0x800, flags, &sc->cfg_handle); in tegra_pcbib_map_cfg()
409 device_printf(sc->dev, "Cannot map config space\n"); in tegra_pcbib_map_cfg()
411 sc->cfg_cur_offs = offs; in tegra_pcbib_map_cfg()
430 if ((sc->ports[i] != NULL) && in tegra_pcib_read_config()
431 (sc->ports[i]->port_idx == slot)) { in tegra_pcib_read_config()
432 hndl = sc->ports[i]->cfg_handle; in tegra_pcib_read_config()
443 hndl = sc->cfg_handle; in tegra_pcib_read_config()
447 val = bus_space_read_4(sc->bus_tag, hndl, off & ~3); in tegra_pcib_read_config()
479 if ((sc->ports[i] != NULL) && in tegra_pcib_write_config()
480 (sc->ports[i]->port_idx == slot)) { in tegra_pcib_write_config()
481 hndl = sc->ports[i]->cfg_handle; in tegra_pcib_write_config()
492 hndl = sc->cfg_handle; in tegra_pcib_write_config()
498 bus_space_write_4(sc->bus_tag, hndl, off, val); in tegra_pcib_write_config()
501 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); in tegra_pcib_write_config()
504 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); in tegra_pcib_write_config()
507 val2 = bus_space_read_4(sc->bus_tag, hndl, off & ~3); in tegra_pcib_write_config()
510 bus_space_write_4(sc->bus_tag, hndl, off & ~3, val2); in tegra_pcib_write_config()
520 code = bus_read_4(sc->afi_mem_res, AFI_INTR_CODE) & AFI_INTR_CODE_MASK; in tegra_pci_intr()
521 signature = bus_read_4(sc->afi_mem_res, AFI_INTR_SIGNATURE); in tegra_pci_intr()
522 bus_write_4(sc->afi_mem_res, AFI_INTR_CODE, 0); in tegra_pci_intr()
530 /* -----------------------------------------------------------------------
578 /* --------------------------------------------------------------------------
591 offs = tgi->irq / AFI_MSI_INTR_IN_REG; in tegra_pcib_isrc_mask()
592 bit = 1 << (tgi->irq % AFI_MSI_INTR_IN_REG); in tegra_pcib_isrc_mask()
613 tf = curthread->td_intr_frame; in tegra_pcib_msi_intr()
619 bit = ffs(reg) - 1; in tegra_pcib_msi_intr()
623 tgi = &sc->isrcs[irq]; in tegra_pcib_msi_intr()
624 if (intr_isrc_dispatch(&tgi->isrc, tf) != 0) { in tegra_pcib_msi_intr()
627 device_printf(sc->dev, in tegra_pcib_msi_intr()
643 sc->isrcs = malloc(sizeof(*sc->isrcs) * TEGRA_PCIB_MAX_MSI, M_DEVBUF, in tegra_pcib_msi_attach()
646 name = device_get_nameunit(sc->dev); in tegra_pcib_msi_attach()
648 sc->isrcs[irq].irq = irq; in tegra_pcib_msi_attach()
649 error = intr_isrc_register(&sc->isrcs[irq].isrc, in tegra_pcib_msi_attach()
650 sc->dev, 0, "%s,%u", name, irq); in tegra_pcib_msi_attach()
654 if (intr_msi_register(sc->dev, in tegra_pcib_msi_attach()
655 OF_xref_from_node(ofw_bus_get_node(sc->dev))) != 0) in tegra_pcib_msi_attach()
669 device_printf(sc->dev, "%s: not implemented yet\n", __func__); in tegra_pcib_msi_detach()
695 /* MSI interrupts are edge trigered -> do nothing */
715 if (data == NULL || data->type != INTR_MAP_DATA_MSI) in tegra_pcib_msi_setup_intr()
718 if (isrc->isrc_handlers == 0) in tegra_pcib_msi_setup_intr()
734 if (isrc->isrc_handlers == 0) in tegra_pcib_msi_teardown_intr()
751 mtx_lock(&sc->mtx); in tegra_pcib_msi_alloc_msi()
754 for (irq = 0; (irq + count - 1) < TEGRA_PCIB_MAX_MSI; irq++) { in tegra_pcib_msi_alloc_msi()
756 if ((irq & (maxcount - 1)) != 0) in tegra_pcib_msi_alloc_msi()
765 if ((sc->isrcs[end_irq].flags & TEGRA_FLAG_MSI_USED) == in tegra_pcib_msi_alloc_msi()
777 if (!found || irq == (TEGRA_PCIB_MAX_MSI - 1)) { in tegra_pcib_msi_alloc_msi()
778 mtx_unlock(&sc->mtx); in tegra_pcib_msi_alloc_msi()
784 sc->isrcs[irq + i].flags |= TEGRA_FLAG_MSI_USED; in tegra_pcib_msi_alloc_msi()
786 mtx_unlock(&sc->mtx); in tegra_pcib_msi_alloc_msi()
789 srcs[i] = (struct intr_irqsrc *)&sc->isrcs[irq + i]; in tegra_pcib_msi_alloc_msi()
803 mtx_lock(&sc->mtx); in tegra_pcib_msi_release_msi()
807 KASSERT((ti->flags & TEGRA_FLAG_MSI_USED) == TEGRA_FLAG_MSI_USED, in tegra_pcib_msi_release_msi()
808 ("%s: Trying to release an unused MSI-X interrupt", in tegra_pcib_msi_release_msi()
811 ti->flags &= ~TEGRA_FLAG_MSI_USED; in tegra_pcib_msi_release_msi()
813 mtx_unlock(&sc->mtx); in tegra_pcib_msi_release_msi()
824 *addr = vtophys(sc->msi_page); in tegra_pcib_msi_map_msi()
825 *data = ti->irq; in tegra_pcib_msi_map_msi()
830 /* ------------------------------------------------------------------- */
851 rv = hwreset_assert(sc->hwreset_pcie_x); in tegra_pcib_enable_fdt_resources()
853 device_printf(sc->dev, "Cannot assert 'pcie_x' reset\n"); in tegra_pcib_enable_fdt_resources()
856 rv = hwreset_assert(sc->hwreset_afi); in tegra_pcib_enable_fdt_resources()
858 device_printf(sc->dev, "Cannot assert 'afi' reset\n"); in tegra_pcib_enable_fdt_resources()
861 rv = hwreset_assert(sc->hwreset_pex); in tegra_pcib_enable_fdt_resources()
863 device_printf(sc->dev, "Cannot assert 'pex' reset\n"); in tegra_pcib_enable_fdt_resources()
870 for (i = 0; i < nitems(sc->regulators); i++) { in tegra_pcib_enable_fdt_resources()
871 if (sc->regulators[i] == NULL) in tegra_pcib_enable_fdt_resources()
873 rv = regulator_enable(sc->regulators[i]); in tegra_pcib_enable_fdt_resources()
875 device_printf(sc->dev, in tegra_pcib_enable_fdt_resources()
877 sc->soc->regulator_names[i]); in tegra_pcib_enable_fdt_resources()
883 sc->clk_pex, sc->hwreset_pex); in tegra_pcib_enable_fdt_resources()
885 device_printf(sc->dev, "Cannot enable 'PCX' powergate\n"); in tegra_pcib_enable_fdt_resources()
889 rv = hwreset_deassert(sc->hwreset_afi); in tegra_pcib_enable_fdt_resources()
891 device_printf(sc->dev, "Cannot unreset 'afi' reset\n"); in tegra_pcib_enable_fdt_resources()
895 rv = clk_enable(sc->clk_afi); in tegra_pcib_enable_fdt_resources()
897 device_printf(sc->dev, "Cannot enable 'afi' clock\n"); in tegra_pcib_enable_fdt_resources()
900 if (sc->soc->cml_clk) { in tegra_pcib_enable_fdt_resources()
901 rv = clk_enable(sc->clk_cml); in tegra_pcib_enable_fdt_resources()
903 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); in tegra_pcib_enable_fdt_resources()
907 rv = clk_enable(sc->clk_pll_e); in tegra_pcib_enable_fdt_resources()
909 device_printf(sc->dev, "Cannot enable 'pll_e' clock\n"); in tegra_pcib_enable_fdt_resources()
929 port->enabled = 1; in tegra_pcib_parse_port()
931 port->enabled = 0; in tegra_pcib_parse_port()
933 rv = OF_getencprop(node, "assigned-addresses", tmp, sizeof(tmp)); in tegra_pcib_parse_port()
935 device_printf(sc->dev, "Cannot parse assigned-address: %d\n", in tegra_pcib_parse_port()
939 port->rp_base_addr = tmp[2]; in tegra_pcib_parse_port()
940 port->rp_size = tmp[4]; in tegra_pcib_parse_port()
941 port->port_idx = OFW_PCI_PHYS_HI_DEVICE(tmp[0]) - 1; in tegra_pcib_parse_port()
942 if (port->port_idx >= TEGRA_PCIB_MAX_PORTS) { in tegra_pcib_parse_port()
943 device_printf(sc->dev, "Invalid port index: %d\n", in tegra_pcib_parse_port()
944 port->port_idx); in tegra_pcib_parse_port()
947 /* XXX - TODO: in tegra_pcib_parse_port()
949 * - it have PCI bus format in tegra_pcib_parse_port()
950 * - its relative to matching "assigned-addresses" in tegra_pcib_parse_port()
954 device_printf(sc->dev, "Cannot parse reg: %d\n", rv); in tegra_pcib_parse_port()
957 port->rp_base_addr += tmp[2]; in tegra_pcib_parse_port()
959 rv = OF_getencprop(node, "nvidia,num-lanes", &port->num_lanes, in tegra_pcib_parse_port()
960 sizeof(port->num_lanes)); in tegra_pcib_parse_port()
961 if (rv != sizeof(port->num_lanes)) { in tegra_pcib_parse_port()
962 device_printf(sc->dev, "Cannot parse nvidia,num-lanes: %d\n", in tegra_pcib_parse_port()
966 if (port->num_lanes > 4) { in tegra_pcib_parse_port()
967 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", in tegra_pcib_parse_port()
968 port->num_lanes); in tegra_pcib_parse_port()
972 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); in tegra_pcib_parse_port()
973 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); in tegra_pcib_parse_port()
976 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); in tegra_pcib_parse_port()
978 device_printf(sc->dev, in tegra_pcib_parse_port()
979 "Cannot get 'pcie-0' phy for port %d\n", in tegra_pcib_parse_port()
980 port->port_idx); in tegra_pcib_parse_port()
998 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { in tegra_pcib_parse_fdt_resources()
999 if (i >= nitems(sc->regulators)) { in tegra_pcib_parse_fdt_resources()
1000 device_printf(sc->dev, in tegra_pcib_parse_fdt_resources()
1004 rv = regulator_get_by_ofw_property(sc->dev, 0, in tegra_pcib_parse_fdt_resources()
1005 sc->soc->regulator_names[i], sc->regulators + i); in tegra_pcib_parse_fdt_resources()
1007 device_printf(sc->dev, in tegra_pcib_parse_fdt_resources()
1009 sc->soc->regulator_names[i]); in tegra_pcib_parse_fdt_resources()
1015 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pex", &sc->hwreset_pex); in tegra_pcib_parse_fdt_resources()
1017 device_printf(sc->dev, "Cannot get 'pex' reset\n"); in tegra_pcib_parse_fdt_resources()
1020 rv = hwreset_get_by_ofw_name(sc->dev, 0, "afi", &sc->hwreset_afi); in tegra_pcib_parse_fdt_resources()
1022 device_printf(sc->dev, "Cannot get 'afi' reset\n"); in tegra_pcib_parse_fdt_resources()
1025 rv = hwreset_get_by_ofw_name(sc->dev, 0, "pcie_x", &sc->hwreset_pcie_x); in tegra_pcib_parse_fdt_resources()
1027 device_printf(sc->dev, "Cannot get 'pcie_x' reset\n"); in tegra_pcib_parse_fdt_resources()
1032 rv = clk_get_by_ofw_name(sc->dev, 0, "pex", &sc->clk_pex); in tegra_pcib_parse_fdt_resources()
1034 device_printf(sc->dev, "Cannot get 'pex' clock\n"); in tegra_pcib_parse_fdt_resources()
1037 rv = clk_get_by_ofw_name(sc->dev, 0, "afi", &sc->clk_afi); in tegra_pcib_parse_fdt_resources()
1039 device_printf(sc->dev, "Cannot get 'afi' clock\n"); in tegra_pcib_parse_fdt_resources()
1042 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); in tegra_pcib_parse_fdt_resources()
1044 device_printf(sc->dev, "Cannot get 'pll_e' clock\n"); in tegra_pcib_parse_fdt_resources()
1047 if (sc->soc->cml_clk) { in tegra_pcib_parse_fdt_resources()
1048 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); in tegra_pcib_parse_fdt_resources()
1050 device_printf(sc->dev, "Cannot get 'cml' clock\n"); in tegra_pcib_parse_fdt_resources()
1056 sc->num_ports = 0; in tegra_pcib_parse_fdt_resources()
1060 device_printf(sc->dev, "Cannot parse PCIe port node\n"); in tegra_pcib_parse_fdt_resources()
1063 sc->ports[sc->num_ports++] = port; in tegra_pcib_parse_fdt_resources()
1078 if (sc->io_range.size != 0) { in tegra_pcib_decode_ranges()
1079 device_printf(sc->dev, in tegra_pcib_decode_ranges()
1083 sc->io_range = ranges[i]; in tegra_pcib_decode_ranges()
1088 if (sc->pref_mem_range.size != 0) { in tegra_pcib_decode_ranges()
1089 device_printf(sc->dev, in tegra_pcib_decode_ranges()
1094 sc->pref_mem_range = ranges[i]; in tegra_pcib_decode_ranges()
1096 if (sc->mem_range.size != 0) { in tegra_pcib_decode_ranges()
1097 device_printf(sc->dev, in tegra_pcib_decode_ranges()
1102 sc->mem_range = ranges[i]; in tegra_pcib_decode_ranges()
1106 if ((sc->io_range.size == 0) || (sc->mem_range.size == 0) in tegra_pcib_decode_ranges()
1107 || (sc->pref_mem_range.size == 0)) { in tegra_pcib_decode_ranges()
1108 device_printf(sc->dev, in tegra_pcib_decode_ranges()
1126 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, in tegra_pcib_wait_for_link()
1130 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, in tegra_pcib_wait_for_link()
1133 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { in tegra_pcib_wait_for_link()
1134 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, in tegra_pcib_wait_for_link()
1143 for (i = TEGRA_PCIE_LINKUP_TIMEOUT; i > 0; i--) { in tegra_pcib_wait_for_link()
1144 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, in tegra_pcib_wait_for_link()
1163 port = sc->ports[port_num]; in tegra_pcib_port_enable()
1166 reg = AFI_RD4(sc, port->afi_pex_ctrl); in tegra_pcib_port_enable()
1168 AFI_WR4(sc, port->afi_pex_ctrl, reg); in tegra_pcib_port_enable()
1169 AFI_RD4(sc, port->afi_pex_ctrl); in tegra_pcib_port_enable()
1176 AFI_WR4(sc, port->afi_pex_ctrl, reg); in tegra_pcib_port_enable()
1177 AFI_RD4(sc, port->afi_pex_ctrl); in tegra_pcib_port_enable()
1182 AFI_WR4(sc, port->afi_pex_ctrl, reg); in tegra_pcib_port_enable()
1184 if (sc->soc->pca_enable) { in tegra_pcib_port_enable()
1185 reg = tegra_pcib_read_config(sc->dev, 0, port->port_idx, 0, in tegra_pcib_port_enable()
1188 tegra_pcib_write_config(sc->dev, 0, port->port_idx, 0, in tegra_pcib_port_enable()
1194 device_printf(sc->dev, " port %d (%d lane%s): Link is %s\n", in tegra_pcib_port_enable()
1195 port->port_idx, port->num_lanes, in tegra_pcib_port_enable()
1196 port->num_lanes > 1 ? "s": "", in tegra_pcib_port_enable()
1206 port = sc->ports[port_num]; in tegra_pcib_port_disable()
1209 reg = AFI_RD4(sc, port->afi_pex_ctrl); in tegra_pcib_port_disable()
1211 AFI_WR4(sc, port->afi_pex_ctrl, reg); in tegra_pcib_port_disable()
1212 AFI_RD4(sc, port->afi_pex_ctrl); in tegra_pcib_port_disable()
1218 AFI_WR4(sc, port->afi_pex_ctrl, reg); in tegra_pcib_port_disable()
1221 device_printf(sc->dev, " port %d (%d lane%s): Disabled\n", in tegra_pcib_port_disable()
1222 port->port_idx, port->num_lanes, in tegra_pcib_port_disable()
1223 port->num_lanes > 1 ? "s": ""); in tegra_pcib_port_disable()
1252 device_printf(sc->dev, "Cannot enable FDT resources\n"); in tegra_pcib_enable()
1268 if (sc->lanes_cfg == 0x14) { in tegra_pcib_enable()
1270 device_printf(sc->dev, in tegra_pcib_enable()
1273 } else if (sc->lanes_cfg == 0x12) { in tegra_pcib_enable()
1275 device_printf(sc->dev, in tegra_pcib_enable()
1279 device_printf(sc->dev, in tegra_pcib_enable()
1280 "Unsupported lanes configuration: 0x%X\n", sc->lanes_cfg); in tegra_pcib_enable()
1284 if ((sc->ports[i] != NULL)) in tegra_pcib_enable()
1286 ~AFI_PCIE_CONFIG_PCIE_DISABLE(sc->ports[i]->port_idx); in tegra_pcib_enable()
1296 if (sc->ports[i] != NULL) { in tegra_pcib_enable()
1297 rv = phy_enable(sc->ports[i]->phy); in tegra_pcib_enable()
1299 device_printf(sc->dev, in tegra_pcib_enable()
1301 sc->ports[i]->port_idx); in tegra_pcib_enable()
1308 PADS_WR4(sc, PADS_REFCLK_CFG0, sc->soc->pads_refclk_cfg0); in tegra_pcib_enable()
1309 if (sc->num_ports > 2) in tegra_pcib_enable()
1310 PADS_WR4(sc, PADS_REFCLK_CFG1, sc->soc->pads_refclk_cfg1); in tegra_pcib_enable()
1312 rv = hwreset_deassert(sc->hwreset_pcie_x); in tegra_pcib_enable()
1314 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); in tegra_pcib_enable()
1349 /* BAR 0 - type 1 extended configuration. */ in tegra_pcib_enable()
1350 tegra_pcib_set_bar(sc, 0, rman_get_start(sc->cfg_mem_res), in tegra_pcib_enable()
1351 FPCI_MAP_EXT_TYPE1_CONFIG, rman_get_size(sc->cfg_mem_res), 0); in tegra_pcib_enable()
1353 /* BAR 1 - downstream I/O. */ in tegra_pcib_enable()
1354 tegra_pcib_set_bar(sc, 1, sc->io_range.host, FPCI_MAP_IO, in tegra_pcib_enable()
1355 sc->io_range.size, 0); in tegra_pcib_enable()
1357 /* BAR 2 - downstream prefetchable memory 1:1. */ in tegra_pcib_enable()
1358 tegra_pcib_set_bar(sc, 2, sc->pref_mem_range.host, in tegra_pcib_enable()
1359 sc->pref_mem_range.host, sc->pref_mem_range.size, 1); in tegra_pcib_enable()
1361 /* BAR 3 - downstream not prefetchable memory 1:1 .*/ in tegra_pcib_enable()
1362 tegra_pcib_set_bar(sc, 3, sc->mem_range.host, in tegra_pcib_enable()
1363 sc->mem_range.host, sc->mem_range.size, 1); in tegra_pcib_enable()
1365 /* BAR 3-8 clear. */ in tegra_pcib_enable()
1372 /* MSI BAR - clear. */ in tegra_pcib_enable()
1387 sc->msi_page = (uintptr_t)kmem_alloc_contig(PAGE_SIZE, M_WAITOK, 0, in tegra_pcib_attach_msi()
1391 tegra_pcib_set_bar(sc, 9, vtophys(sc->msi_page), vtophys(sc->msi_page), in tegra_pcib_attach_msi()
1399 rv = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, in tegra_pcib_attach_msi()
1400 tegra_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); in tegra_pcib_attach_msi()
1429 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { in tegra_pcib_probe()
1430 device_set_desc(dev, "Nvidia Integrated PCI/PCI-E Controller"); in tegra_pcib_probe()
1447 sc->dev = dev; in tegra_pcib_attach()
1448 mtx_init(&sc->mtx, "msi_mtx", NULL, MTX_DEF); in tegra_pcib_attach()
1451 sc->soc = (struct pcie_soc *)ofw_bus_search_compatible(dev, in tegra_pcib_attach()
1452 compat_data)->ocd_data; in tegra_pcib_attach()
1462 sc->pads_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in tegra_pcib_attach()
1464 if (sc->pads_mem_res == NULL) { in tegra_pcib_attach()
1470 * XXX - FIXME in tegra_pcib_attach()
1473 sc->bus_tag = rman_get_bustag(sc->pads_mem_res); in tegra_pcib_attach()
1476 sc->afi_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in tegra_pcib_attach()
1478 if (sc->afi_mem_res == NULL) { in tegra_pcib_attach()
1485 sc->cfg_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in tegra_pcib_attach()
1487 if (sc->cfg_mem_res == NULL) { in tegra_pcib_attach()
1492 sc->cfg_base_addr = rman_get_start(sc->cfg_mem_res); in tegra_pcib_attach()
1496 if (sc->ports[i] == NULL) in tegra_pcib_attach()
1498 port = sc->ports[i]; in tegra_pcib_attach()
1499 rv = bus_space_map(sc->bus_tag, port->rp_base_addr, in tegra_pcib_attach()
1500 port->rp_size, 0, &port->cfg_handle); in tegra_pcib_attach()
1502 device_printf(sc->dev, "Cannot allocate memory for " in tegra_pcib_attach()
1513 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in tegra_pcib_attach()
1515 if (sc->irq_res == NULL) { in tegra_pcib_attach()
1522 sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, in tegra_pcib_attach()
1524 if (sc->irq_res == NULL) { in tegra_pcib_attach()
1530 sc->ofw_pci.sc_range_mask = 0x3; in tegra_pcib_attach()
1535 rv = tegra_pcib_decode_ranges(sc, sc->ofw_pci.sc_range, in tegra_pcib_attach()
1536 sc->ofw_pci.sc_nrange); in tegra_pcib_attach()
1540 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, in tegra_pcib_attach()
1541 tegra_pci_intr, NULL, sc, &sc->intr_cookie)) { in tegra_pcib_attach()
1554 if (sc->ports[i] == NULL) in tegra_pcib_attach()
1556 if (sc->ports[i]->enabled) in tegra_pcib_attach()
1597 /* MSI/MSI-X */