59 #define	SATA_CONFIGURATION			0x180
61 #define	 SATA_CONFIGURATION_EN_FPCI			(1  <<  0)
63 #define	SATA_FPCI_BAR5				0x94
64 #define	 SATA_FPCI_BAR_START(x)				(((x) & 0xFFFFFFF) << 4)
65 #define	 SATA_FPCI_BAR_ACCESS_TYPE			(1 << 0)
67 #define	SATA_INTR_MASK				0x188
70 #define	SCFG_OFFSET				0x1000
72 #define	T_SATA0_CFG_1				0x04
73 #define	 T_SATA0_CFG_1_IO_SPACE				(1 << 0)
78 #define	T_SATA0_CFG_9				0x24
81 #define	T_SATA0_CFG_35				0x94
82 #define	 T_SATA0_CFG_35_IDP_INDEX_MASK			(0x7ff << 2)
83 #define	 T_SATA0_CFG_35_IDP_INDEX			(0x2a << 2)
85 #define	T_SATA0_AHCI_IDP1			0x98
86 #define	 T_SATA0_AHCI_IDP1_DATA				0x400040
88 #define	T_SATA0_CFG_PHY_1			0x12c
92 #define	T_SATA0_NVOOB				0x114
93 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK	(0x3 << 26)
94 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH		(0x3 << 26)
95 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK		(0x3 << 24)
96 #define	 T_SATA0_NVOOB_SQUELCH_FILTER_MODE		(0x1 << 24)
97 #define	 T_SATA0_NVOOB_COMMA_CNT_MASK			(0xff << 16)
98 #define	 T_SATA0_NVOOB_COMMA_CNT			(0x07 << 16)
100 #define	T_SATA0_CFG_PHY				0x120
104 #define	T_SATA0_CFG2NVOOB_2			0x134
105 #define	 T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK	(0x1ff << 18)
106 #define	 T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW	(0xc << 18)
108 #define	T_SATA0_AHCI_HBA_CAP_BKDR		0x300
115 #define	T_SATA0_BKDOOR_CC			0x4a4
116 #define	 T_SATA0_BKDOOR_CC_CLASS_CODE_MASK		(0xffff << 16)
117 #define	 T_SATA0_BKDOOR_CC_CLASS_CODE			(0x0106 << 16)
118 #define	 T_SATA0_BKDOOR_CC_PROG_IF_MASK			(0xff << 8)
119 #define	 T_SATA0_BKDOOR_CC_PROG_IF			(0x01 << 8)
121 #define	T_SATA0_CFG_SATA			0x54c
124 #define	T_SATA0_CFG_MISC			0x550
125 #define	T_SATA0_INDEX				0x680
127 #define	T_SATA0_CHX_PHY_CTRL1_GEN1		0x690
128 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK	0xff
130 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK		0xff
131 #define	 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT	0
133 #define	T_SATA0_CHX_PHY_CTRL1_GEN2		0x694
134 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK	0xff
136 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK		0xff
137 #define	 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT	0
139 #define	T_SATA0_CHX_PHY_CTRL2			0x69c
140 #define	 T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1		0x23
142 #define	T_SATA0_CHX_PHY_CTRL11			0x6d0
143 #define	 T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ		(0x2800 << 16)
145 #define T_SATA0_CHX_PHY_CTRL17			0x6e8
146 #define T_SATA0_CHX_PHY_CTRL18			0x6ec
147 #define T_SATA0_CHX_PHY_CTRL20			0x6f4
148 #define T_SATA0_CHX_PHY_CTRL21			0x6f8
150 #define	FUSE_SATA_CALIB				0x124
151 #define	FUSE_SATA_CALIB_MASK			0x3
153 #define	SATA_AUX_MISC_CNTL			0x1108
154 #define	SATA_AUX_PAD_PLL_CTRL_0			0x1120
155 #define	SATA_AUX_PAD_PLL_CTRL_1			0x1124
156 #define	SATA_AUX_PAD_PLL_CTRL_2			0x1128
157 #define	SATA_AUX_PAD_PLL_CTRL_3			0x112c
159 #define	T_AHCI_HBA_CCC_PORTS			0x0018
160 #define	T_AHCI_HBA_CAP_BKDR			0x00A0
169 #define	 T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x)		(((x) & 0xF) << 20)
177 #define	 T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x)		(((x) & 0x1F) <<  8)
181 #define	 T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x)		(((x) & 0xF) <<  0)
183 #define	T_AHCI_PORT_BKDR			0x0170
185 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x)	(((x) & 0xFF) << 24)
186 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x)	(((x) & 0x1F) << 16)
189 #define	 T_AHCI_PORT_BKDR_PXDEVSLP_DM(x)		(((x) & 0xF) << 10)
199 #define	 T_AHCI_PORT_BKDR_EXT_SATA_SUPP			(1 <<  0)
202 #define	SATA_AUX_MISC_CNTL_1			0x008
220 	{0x18, 0x04, 0x18, 0x0a},
221 	{0x0e, 0x04, 0x14, 0x0a},
222 	{0x0e, 0x07, 0x1a, 0x0e},
223 	{0x14, 0x0e, 0x1a, 0x0e},
278 	{NULL,			0}
287 	for (i = 0; sc->soc->regulator_names[i] != NULL; i++) {  in get_fdt_resources()
293 		rv = regulator_get_by_ofw_property(sc->dev, 0,  in get_fdt_resources()
295 		if (rv != 0) {  in get_fdt_resources()
304 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata );  in get_fdt_resources()
305 	if (rv != 0) {  in get_fdt_resources()
309 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob",  in get_fdt_resources()
311 	if (rv != 0) {  in get_fdt_resources()
315 	rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold",  in get_fdt_resources()
317 	if (rv != 0) {  in get_fdt_resources()
323 	rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy);  in get_fdt_resources()
324 	if (rv != 0) {  in get_fdt_resources()
325 		rv = phy_get_by_ofw_idx(sc->dev, 0, 0, &sc->phy);  in get_fdt_resources()
326 		if (rv != 0) {  in get_fdt_resources()
333 	rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata);  in get_fdt_resources()
334 	if (rv != 0) {  in get_fdt_resources()
338 	rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob);  in get_fdt_resources()
339 	if (rv != 0) {  in get_fdt_resources()
344 	rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml);  in get_fdt_resources()
345 	if (rv != 0)  in get_fdt_resources()
348 	rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);  in get_fdt_resources()
349 	if (rv != 0)  in get_fdt_resources()
351 	return (0);  in get_fdt_resources()
360 	for (i = 0; i < nitems(sc->regulators); i++) {  in enable_fdt_resources()
364 		if (rv != 0) {  in enable_fdt_resources()
378 	if (rv != 0) {  in enable_fdt_resources()
383 	if (rv != 0) {  in enable_fdt_resources()
389 	if (rv != 0) {  in enable_fdt_resources()
395 	if (rv != 0) {  in enable_fdt_resources()
401 	if (rv != 0) {  in enable_fdt_resources()
407 		if (rv != 0) {  in enable_fdt_resources()
414 		if (rv != 0) {  in enable_fdt_resources()
421 	if (rv != 0) {  in enable_fdt_resources()
426 	if (rv != 0) {  in enable_fdt_resources()
432 	if (rv != 0) {  in enable_fdt_resources()
437 	return (0);  in enable_fdt_resources()
475 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0);  in tegra124_ahci_init()
477 	return (0);  in tegra124_ahci_init()
488 	val &= ~SATA_FPCI_BAR_START(~0);  in tegra_ahci_ctrl_init()
489 	val |= SATA_FPCI_BAR_START(0x10000);  in tegra_ahci_ctrl_init()
499 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17, 0x55010000);  in tegra_ahci_ctrl_init()
500 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18, 0x55010000);  in tegra_ahci_ctrl_init()
501 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20, 0x1);  in tegra_ahci_ctrl_init()
502 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21, 0x1);  in tegra_ahci_ctrl_init()
527 		if (rv != 0) {  in tegra_ahci_ctrl_init()
566 	SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_IDP1, 0x400040);  in tegra_ahci_ctrl_init()
599 	    0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT);  in tegra_ahci_ctrl_init()
606 	return (0);  in tegra_ahci_ctrl_init()
618 	if (rv != 0)  in tegra_ahci_ctlr_reset()
619 		return (0);  in tegra_ahci_ctlr_reset()
624 	reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0);  in tegra_ahci_ctlr_reset()
625 	reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0);  in tegra_ahci_ctlr_reset()
641 	return (0);  in tegra_ahci_ctlr_reset()
673 	ctlr->r_rid = 0;  in tegra_ahci_attach()
693 	if (rv != 0) {  in tegra_ahci_attach()
699 	if (rv != 0) {  in tegra_ahci_attach()
704 	if (rv != 0) {  in tegra_ahci_attach()
710 	ctlr->msi = 0;  in tegra_ahci_attach()
712 	ctlr->ccc = 0;  in tegra_ahci_attach()
716 	if (rv != 0)  in tegra_ahci_attach()
736 	return (0);  in tegra_ahci_detach()
748 	return (0);  in tegra_ahci_suspend()
756 	if ((res = tegra_ahci_ctlr_reset(dev)) != 0)  in tegra_ahci_resume()