Lines Matching +full:pwr +full:- +full:reg
1 /*-
135 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
136 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
138 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
139 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
140 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
141 device_get_nameunit(_sc->dev), "tegra124_pmc", MTX_DEF)
142 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
143 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
144 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
168 {"nvidia,tegra124-pmc", 1},
186 uint32_t reg; in tegra124_pmc_set_powergate() local
191 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id); in tegra124_pmc_set_powergate()
192 if (((reg != 0) && ena) || ((reg == 0) && !ena)) { in tegra124_pmc_set_powergate()
197 for (i = 100; i > 0; i--) { in tegra124_pmc_set_powergate()
198 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
199 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) in tegra124_pmc_set_powergate()
204 device_printf(sc->dev, in tegra124_pmc_set_powergate()
210 for (i = 100; i > 0; i--) { in tegra124_pmc_set_powergate()
211 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra124_pmc_set_powergate()
212 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) in tegra124_pmc_set_powergate()
217 device_printf(sc->dev, in tegra124_pmc_set_powergate()
227 uint32_t reg; in tegra_powergate_remove_clamping() local
238 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
239 if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0) in tegra_powergate_remove_clamping()
250 for (i = 100; i > 0; i--) { in tegra_powergate_remove_clamping()
251 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); in tegra_powergate_remove_clamping()
252 if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0) in tegra_powergate_remove_clamping()
257 device_printf(sc->dev, "Timeout when remove clamping\n"); in tegra_powergate_remove_clamping()
259 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
260 if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0) in tegra_powergate_remove_clamping()
270 uint32_t reg; in tegra_powergate_is_powered() local
274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
275 return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0); in tegra_powergate_is_powered()
288 device_printf(sc->dev, "Cannot set powergate: %d\n", id); in tegra_powergate_power_on()
292 for (i = 100; i > 0; i--) { in tegra_powergate_power_on()
298 device_printf(sc->dev, "Timeout when waiting on power up\n"); in tegra_powergate_power_on()
313 device_printf(sc->dev, "Cannot set powergate: %d\n", id); in tegra_powergate_power_off()
316 for (i = 100; i > 0; i--) { in tegra_powergate_power_off()
322 device_printf(sc->dev, "Timeout when waiting on power off\n"); in tegra_powergate_power_off()
338 device_printf(sc->dev, "Cannot assert reset\n"); in tegra_powergate_sequence_power_up()
344 device_printf(sc->dev, "Cannot stop clock\n"); in tegra_powergate_sequence_power_up()
350 device_printf(sc->dev, "Cannot power on powergate\n"); in tegra_powergate_sequence_power_up()
356 device_printf(sc->dev, "Cannot enable clock\n"); in tegra_powergate_sequence_power_up()
363 device_printf(sc->dev, "Cannot remove clamping\n"); in tegra_powergate_sequence_power_up()
368 device_printf(sc->dev, "Cannot unreset reset\n"); in tegra_powergate_sequence_power_up()
388 rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp)); in tegra124_pmc_parse_fdt()
392 sc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra124_pmc_parse_fdt()
396 sc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra124_pmc_parse_fdt()
400 sc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra124_pmc_parse_fdt()
404 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra124_pmc_parse_fdt()
409 rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp)); in tegra124_pmc_parse_fdt()
411 sc->cpu_good_time = tmp; in tegra124_pmc_parse_fdt()
412 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra124_pmc_parse_fdt()
415 rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp)); in tegra124_pmc_parse_fdt()
417 sc->cpu_off_time = tmp; in tegra124_pmc_parse_fdt()
418 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra124_pmc_parse_fdt()
421 rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr, in tegra124_pmc_parse_fdt()
424 sc->core_osc_time = tmparr[0]; in tegra124_pmc_parse_fdt()
425 sc->core_pmu_time = tmparr[1]; in tegra124_pmc_parse_fdt()
426 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra124_pmc_parse_fdt()
429 rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp)); in tegra124_pmc_parse_fdt()
431 sc->core_off_time = tmp; in tegra124_pmc_parse_fdt()
432 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra124_pmc_parse_fdt()
435 sc->corereq_high = in tegra124_pmc_parse_fdt()
436 OF_hasprop(node, "nvidia,core-power-req-active-high"); in tegra124_pmc_parse_fdt()
437 sc->sysclkreq_high = in tegra124_pmc_parse_fdt()
438 OF_hasprop(node, "nvidia,sys-clock-req-active-high"); in tegra124_pmc_parse_fdt()
439 sc->combined_req = in tegra124_pmc_parse_fdt()
440 OF_hasprop(node, "nvidia,combined-power-req"); in tegra124_pmc_parse_fdt()
441 sc->cpu_pwr_good_en = in tegra124_pmc_parse_fdt()
442 OF_hasprop(node, "nvidia,cpu-pwr-good-en"); in tegra124_pmc_parse_fdt()
444 rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr)); in tegra124_pmc_parse_fdt()
446 sc->lp0_vec_phys = tmparr[0]; in tegra124_pmc_parse_fdt()
447 sc->core_pmu_time = tmparr[1]; in tegra124_pmc_parse_fdt()
448 sc->lp0_vec_size = TEGRA_SUSPEND_NONE; in tegra124_pmc_parse_fdt()
449 if (sc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra124_pmc_parse_fdt()
450 sc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra124_pmc_parse_fdt()
462 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in tegra124_pmc_probe()
482 uint32_t reg; in tegra124_pmc_attach() local
486 sc->dev = dev; in tegra124_pmc_attach()
491 device_printf(sc->dev, "Cannot parse FDT data\n"); in tegra124_pmc_attach()
495 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk); in tegra124_pmc_attach()
497 device_printf(sc->dev, "Cannot get \"pclk\" clock\n"); in tegra124_pmc_attach()
502 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in tegra124_pmc_attach()
504 if (sc->mem_res == NULL) { in tegra124_pmc_attach()
512 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
513 reg |= PMC_CNTRL_CPU_PWRREQ_OE; in tegra124_pmc_attach()
514 WR4(sc, PMC_CNTRL, reg); in tegra124_pmc_attach()
517 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
518 if (sc->sysclkreq_high) in tegra124_pmc_attach()
519 reg &= ~PMC_CNTRL_SYSCLK_POLARITY; in tegra124_pmc_attach()
521 reg |= PMC_CNTRL_SYSCLK_POLARITY; in tegra124_pmc_attach()
522 WR4(sc, PMC_CNTRL, reg); in tegra124_pmc_attach()
525 reg = RD4(sc, PMC_CNTRL); in tegra124_pmc_attach()
526 reg |= PMC_CNTRL_SYSCLK_OE; in tegra124_pmc_attach()
527 WR4(sc, PMC_CNTRL, reg); in tegra124_pmc_attach()
533 reg = RD4(sc, PMC_IO_DPD_STATUS); in tegra124_pmc_attach()
534 reg &= ~ PMC_IO_DPD_STATUS_HDMI; in tegra124_pmc_attach()
535 WR4(sc, PMC_IO_DPD_STATUS, reg); in tegra124_pmc_attach()
537 reg = RD4(sc, PMC_IO_DPD2_STATUS); in tegra124_pmc_attach()
538 reg &= ~ PMC_IO_DPD2_STATUS_HV; in tegra124_pmc_attach()
539 WR4(sc, PMC_IO_DPD2_STATUS, reg); in tegra124_pmc_attach()