1 /*-
73 	{ 204000000ULL,	1112619, -29295, 402},
74 	{ 306000000ULL,	1150460, -30585, 402},
75 	{ 408000000ULL,	1190122, -31865, 402},
76 	{ 510000000ULL,	1231606, -33155, 402},
77 	{ 612000000ULL,	1274912, -34435, 402},
78 	{ 714000000ULL,	1320040, -35725, 402},
79 	{ 816000000ULL,	1366990, -37005, 402},
80 	{ 918000000ULL,	1415762, -38295, 402},
81 	{1020000000ULL,	1466355, -39575, 402},
82 	{1122000000ULL,	1518771, -40865, 402},
83 	{1224000000ULL,	1573009, -42145, 402},
84 	{1326000000ULL,	1629068, -43435, 402},
85 	{1428000000ULL,	1686950, -44715, 402},
86 	{1530000000ULL,	1746653, -46005, 402},
87 	{1632000000ULL,	1808179, -47285, 402},
88 	{1734000000ULL,	1871526, -48575, 402},
89 	{1836000000ULL,	1936696, -49855, 402},
90 	{1938000000ULL,	2003687, -51145, 402},
91 	{2014500000ULL,	2054787, -52095, 402},
92 	{2116500000ULL,	2124957, -53385, 402},
93 	{2218500000ULL,	2196950, -54665, 402},
94 	{2320500000ULL,	2270765, -55955, 402},
95 	{2320500000ULL,	2270765, -55955, 402},
96 	{2422500000ULL,	2346401, -57235, 402},
97 	{2524500000ULL,	2437299, -58535, 402},
216  * Compute requesetd voltage for given frequency and SoC process variations,
217  * - compute base voltage from speedo value using speedo table
218  * - round up voltage to next regulator step
219  * - clamp it to regulator limits
230 	for (i = 0; i < sc->cpu_def->speedo_nitems; i++) {  in freq_to_voltage()
231 		if (sc->cpu_def->speedo_tbl[i].freq >= freq) {  in freq_to_voltage()
232 			ent = &sc->cpu_def->speedo_tbl[i];  in freq_to_voltage()
237 		ent = &sc->cpu_def->speedo_tbl[sc->cpu_def->speedo_nitems - 1];  in freq_to_voltage()
238 	scale = sc->cpu_def->speedo_scale;  in freq_to_voltage()
241 	uv = DIV_ROUND_CLOSEST(ent->c2 * sc->speedo_value, scale);  in freq_to_voltage()
242 	uv = DIV_ROUND_CLOSEST((uv + ent->c1) * sc->speedo_value, scale) +  in freq_to_voltage()
243 	    ent->c0;  in freq_to_voltage()
244 	step_uvolt = sc->cpu_def->step_uvolt;  in freq_to_voltage()
249 	min_uvolt = ROUND_UP(sc->cpu_def->min_uvolt, step_uvolt);  in freq_to_voltage()
250 	max_uvolt = ROUND_DOWN(sc->cpu_def->max_uvolt, step_uvolt);  in freq_to_voltage()
263 	sc->nspeed_points = nitems(cpu_freq_tbl);  in build_speed_points()
264 	sc->speed_points = malloc(sizeof(struct cpu_speed_point) *  in build_speed_points()
265 	    sc->nspeed_points, M_DEVBUF, M_NOWAIT);  in build_speed_points()
266 	for (i = 0; i < sc->nspeed_points; i++) {  in build_speed_points()
267 		sc->speed_points[i].freq = cpu_freq_tbl[i];  in build_speed_points()
268 		sc->speed_points[i].uvolt = freq_to_voltage(sc,  in build_speed_points()
278 	if (sc->speed_points[0].freq >= freq)  in get_speed_point()
279 		return (sc->speed_points + 0);  in get_speed_point()
281 	for (i = 0; i < sc->nspeed_points - 1; i++) {  in get_speed_point()
282 		if (sc->speed_points[i + 1].freq > freq)  in get_speed_point()
283 			return (sc->speed_points + i);  in get_speed_point()
286 	return (sc->speed_points + sc->nspeed_points - 1);  in get_speed_point()
301 	for (i = 0, j = sc->nspeed_points - 1; j >= 0; j--) {  in tegra124_cpufreq_settings()
302 		if (sc->cpu_max_freq < sc->speed_points[j].freq)  in tegra124_cpufreq_settings()
304 		sets[i].freq = sc->speed_points[j].freq / 1000000;  in tegra124_cpufreq_settings()
305 		sets[i].volts = sc->speed_points[j].uvolt / 1000;  in tegra124_cpufreq_settings()
306 		sets[i].lat = sc->latency;  in tegra124_cpufreq_settings()
323 	if (sc->act_speed_point->uvolt < point->uvolt) {  in set_cpu_freq()
325 		rv = regulator_set_voltage(sc->supply_vdd_cpu,  in set_cpu_freq()
326 		    point->uvolt, point->uvolt);  in set_cpu_freq()
333 	rv = clk_set_parent_by_clk(sc->clk_cpu_g, sc->clk_pll_p);  in set_cpu_freq()
335 		device_printf(sc->dev, "Can't set parent to PLLP\n");  in set_cpu_freq()
340 	rv = clk_set_freq(sc->clk_pll_x, point->freq, CLK_SET_ROUND_DOWN);  in set_cpu_freq()
342 		device_printf(sc->dev, "Can't set CPU clock frequency\n");  in set_cpu_freq()
346 	rv = clk_set_parent_by_clk(sc->clk_cpu_g, sc->clk_pll_x);  in set_cpu_freq()
348 		device_printf(sc->dev, "Can't set parent to PLLX\n");  in set_cpu_freq()
352 	if (sc->act_speed_point->uvolt > point->uvolt) {  in set_cpu_freq()
354 		rv = regulator_set_voltage(sc->supply_vdd_cpu,  in set_cpu_freq()
355 		    point->uvolt, point->uvolt);  in set_cpu_freq()
360 	sc->act_speed_point = point;  in set_cpu_freq()
372 	if (cf == NULL || cf->freq < 0)  in tegra124_cpufreq_set()
377 	freq = cf->freq;  in tegra124_cpufreq_set()
381 	if (freq >= sc->cpu_max_freq)  in tegra124_cpufreq_set()
382 		freq = sc->cpu_max_freq;  in tegra124_cpufreq_set()
398 	cf->dev = NULL;  in tegra124_cpufreq_get()
399 	cf->freq = sc->act_speed_point->freq / 1000000;  in tegra124_cpufreq_get()
400 	cf->volts = sc->act_speed_point->uvolt / 1000;  in tegra124_cpufreq_get()
402 	cf->lat = sc->latency;  in tegra124_cpufreq_get()
404 	cf->dev = dev;  in tegra124_cpufreq_get()
426 	parent_dev =  device_get_parent(sc->dev);  in get_fdt_resources()
427 	rv = regulator_get_by_ofw_property(parent_dev, 0, "vdd-cpu-supply",  in get_fdt_resources()
428 	    &sc->supply_vdd_cpu);  in get_fdt_resources()
430 		device_printf(sc->dev, "Cannot get 'vdd-cpu' regulator\n");  in get_fdt_resources()
434 	rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_g", &sc->clk_cpu_g);  in get_fdt_resources()
436 		device_printf(sc->dev, "Cannot get 'cpu_g' clock: %d\n", rv);  in get_fdt_resources()
440 	rv = clk_get_by_ofw_name(parent_dev, 0, "cpu_lp", &sc->clk_cpu_lp);  in get_fdt_resources()
442 		device_printf(sc->dev, "Cannot get 'cpu_lp' clock\n");  in get_fdt_resources()
446 	rv = clk_get_by_ofw_name(parent_dev, 0, "pll_x", &sc->clk_pll_x);  in get_fdt_resources()
448 		device_printf(sc->dev, "Cannot get 'pll_x' clock\n");  in get_fdt_resources()
451 	rv = clk_get_by_ofw_name(parent_dev, 0, "pll_p", &sc->clk_pll_p);  in get_fdt_resources()
456 	rv = clk_get_by_ofw_name(parent_dev, 0, "dfll", &sc->clk_dfll);  in get_fdt_resources()
460 		device_printf(sc->dev, "Cannot get 'dfll' clock\n");  in get_fdt_resources()
478 	if (device_find_child(parent, "tegra124_cpufreq", -1) != NULL)  in tegra124_cpufreq_identify()
480 	if (BUS_ADD_CHILD(parent, 0, "tegra124_cpufreq", -1) == NULL)  in tegra124_cpufreq_identify()
501 	sc->dev = dev;  in tegra124_cpufreq_attach()
502 	sc->node = ofw_bus_get_node(device_get_parent(dev));  in tegra124_cpufreq_attach()
504 	sc->process_id = tegra_sku_info.cpu_process_id;  in tegra124_cpufreq_attach()
505 	sc->speedo_id = tegra_sku_info.cpu_speedo_id;  in tegra124_cpufreq_attach()
506 	sc->speedo_value = tegra_sku_info.cpu_speedo_value;  in tegra124_cpufreq_attach()
511 		sc->cpu_def = &tegra124_cpu_volt_pllx_def;  in tegra124_cpufreq_attach()
513 		sc->cpu_def = &tegra124_cpu_volt_dpll_def;  in tegra124_cpufreq_attach()
515 	rv = get_fdt_resources(sc, sc->node);  in tegra124_cpufreq_attach()
522 	rv = clk_get_freq(sc->clk_cpu_g, &freq);  in tegra124_cpufreq_attach()
527 	if (sc->speedo_id < nitems(cpu_max_freq))  in tegra124_cpufreq_attach()
528 		sc->cpu_max_freq = cpu_max_freq[sc->speedo_id];  in tegra124_cpufreq_attach()
530 		sc->cpu_max_freq = cpu_max_freq[0];  in tegra124_cpufreq_attach()
531 	sc->act_speed_point = get_speed_point(sc, freq);  in tegra124_cpufreq_attach()
554 	if (sc->supply_vdd_cpu != NULL)  in tegra124_cpufreq_detach()
555 		regulator_release(sc->supply_vdd_cpu);  in tegra124_cpufreq_detach()
557 	if (sc->clk_cpu_g != NULL)  in tegra124_cpufreq_detach()
558 		clk_release(sc->clk_cpu_g);  in tegra124_cpufreq_detach()
559 	if (sc->clk_cpu_lp != NULL)  in tegra124_cpufreq_detach()
560 		clk_release(sc->clk_cpu_lp);  in tegra124_cpufreq_detach()
561 	if (sc->clk_pll_x != NULL)  in tegra124_cpufreq_detach()
562 		clk_release(sc->clk_pll_x);  in tegra124_cpufreq_detach()
563 	if (sc->clk_pll_p != NULL)  in tegra124_cpufreq_detach()
564 		clk_release(sc->clk_pll_p);  in tegra124_cpufreq_detach()
565 	if (sc->clk_dfll != NULL)  in tegra124_cpufreq_detach()
566 		clk_release(sc->clk_dfll);  in tegra124_cpufreq_detach()