106 	uint32_t		misc_reg;  member
221 		.misc_reg = PLLM_MISC,
232 		.misc_reg = PLLX_MISC,
245 		.misc_reg = PLLC_MISC,
258 		.misc_reg = PLLC2_MISC,
269 		.misc_reg = PLLC3_MISC,
280 		.misc_reg = PLLC4_MISC,
293 		.misc_reg = PLLP_MISC,
303 		.misc_reg = PLLA_MISC,
313 		.misc_reg = PLLU_MISC,
324 		.misc_reg = PLLD_MISC,
334 		.misc_reg = PLLD2_MISC,
347 		.misc_reg = PLLRE_MISC,
360 		.misc_reg = PLLE_MISC,
370 		.misc_reg = PLLDP_MISC,
390 	uint32_t		misc_reg;  member
521 		RD4(sc, sc->misc_reg, &reg);  in is_locked()
526 		RD4(sc, sc->misc_reg, &reg);  in is_locked()
576 	RD4(sc, sc->misc_reg, &reg);  in plle_enable()
583 	WR4(sc, sc->misc_reg, reg);  in plle_enable()
618 	RD4(sc, sc->misc_reg, &reg);  in plle_enable()
620 	WR4(sc, sc->misc_reg, reg);  in plle_enable()
745 	RD4(sc, sc->misc_reg, &reg);  in pll_set_std()
747 	WR4(sc, sc->misc_reg, reg);  in pll_set_std()
757 	RD4(sc, sc->misc_reg, &reg);  in pll_set_std()
929 	RD4(sc, sc->misc_reg, &reg);  in pllx_set_freq()
931 	WR4(sc, sc->misc_reg, reg);  in pllx_set_freq()
946 	RD4(sc, sc->misc_reg, &reg);  in pllx_set_freq()
1007 		RD4(sc, sc->misc_reg, &reg);  in tegra124_pll_init()
1009 		WR4(sc, sc->misc_reg, reg);  in tegra124_pll_init()
1012 		RD4(sc, sc->misc_reg, &reg);  in tegra124_pll_init()
1014 		WR4(sc, sc->misc_reg, reg);  in tegra124_pll_init()
1026 	uint32_t reg, misc_reg;  in tegra124_pll_recalc()  local
1031 	RD4(sc, sc->misc_reg, &misc_reg);  in tegra124_pll_recalc()
1041 	    clknode_get_name(clk), reg, misc_reg, m, n, p, pr,  in tegra124_pll_recalc()
1067 	sc->misc_reg = clkdef->misc_reg;  in pll_register()