Lines Matching +full:0 +full:x3e0
38 #define RST_DEVICES_L 0x004
39 #define RST_DEVICES_H 0x008
40 #define RST_DEVICES_U 0x00C
41 #define CLK_OUT_ENB_L 0x010
42 #define CLK_OUT_ENB_H 0x014
43 #define CLK_OUT_ENB_U 0x018
44 #define CCLK_BURST_POLICY 0x020
45 #define SUPER_CCLK_DIVIDER 0x024
46 #define SCLK_BURST_POLICY 0x028
47 #define SUPER_SCLK_DIVIDER 0x02c
48 #define CLK_SYSTEM_RATE 0x030
50 #define OSC_CTRL 0x050
54 #define PLLE_SS_CNTL 0x068
55 #define PLLE_SS_CNTL_SSCINCINTRV_MASK (0x3f << 24)
56 #define PLLE_SS_CNTL_SSCINCINTRV_VAL (0x20 << 24)
57 #define PLLE_SS_CNTL_SSCINC_MASK (0xff << 16)
58 #define PLLE_SS_CNTL_SSCINC_VAL (0x1 << 16)
64 #define PLLE_SS_CNTL_SSCMAX_MASK 0x1ff
65 #define PLLE_SS_CNTL_SSCMAX_VAL 0x25
76 #define PLLC_BASE 0x080
77 #define PLLC_OUT 0x084
78 #define PLLC_MISC2 0x088
79 #define PLLC_MISC 0x08c
80 #define PLLM_BASE 0x090
81 #define PLLM_OUT 0x094
82 #define PLLM_MISC 0x09c
83 #define PLLP_BASE 0x0a0
84 #define PLLP_MISC 0x0ac
85 #define PLLP_OUTA 0x0a4
86 #define PLLP_OUTB 0x0a8
87 #define PLLA_BASE 0x0b0
88 #define PLLA_OUT 0x0b4
89 #define PLLA_MISC 0x0bc
90 #define PLLU_BASE 0x0c0
91 #define PLLU_MISC 0x0cc
92 #define PLLD_BASE 0x0d0
93 #define PLLD_MISC 0x0dc
94 #define PLLX_BASE 0x0e0
95 #define PLLX_MISC 0x0e4
96 #define PLLE_BASE 0x0e8
99 #define PLLE_BASE_DIVCML_MASK 0xf
101 #define PLLE_MISC 0x0ec
103 #define PLLE_MISC_SETUP_BASE_MASK (0xffff << PLLE_MISC_SETUP_BASE_SHIFT)
116 #define CLK_SOURCE_I2S1 0x100
117 #define CLK_SOURCE_I2S2 0x104
118 #define CLK_SOURCE_SPDIF_OUT 0x108
119 #define CLK_SOURCE_SPDIF_IN 0x10c
120 #define CLK_SOURCE_PWM 0x110
121 #define CLK_SOURCE_SPI2 0x118
122 #define CLK_SOURCE_SPI3 0x11c
123 #define CLK_SOURCE_I2C1 0x124
124 #define CLK_SOURCE_I2C5 0x128
125 #define CLK_SOURCE_SPI1 0x134
126 #define CLK_SOURCE_DISP1 0x138
127 #define CLK_SOURCE_DISP2 0x13c
128 #define CLK_SOURCE_ISP 0x144
129 #define CLK_SOURCE_VI 0x148
130 #define CLK_SOURCE_SDMMC1 0x150
131 #define CLK_SOURCE_SDMMC2 0x154
132 #define CLK_SOURCE_SDMMC4 0x164
133 #define CLK_SOURCE_VFIR 0x168
134 #define CLK_SOURCE_HSI 0x174
135 #define CLK_SOURCE_UARTA 0x178
136 #define CLK_SOURCE_UARTB 0x17c
137 #define CLK_SOURCE_HOST1X 0x180
138 #define CLK_SOURCE_HDMI 0x18c
139 #define CLK_SOURCE_I2C2 0x198
140 #define CLK_SOURCE_EMC 0x19c
141 #define CLK_SOURCE_UARTC 0x1a0
142 #define CLK_SOURCE_VI_SENSOR 0x1a8
143 #define CLK_SOURCE_SPI4 0x1b4
144 #define CLK_SOURCE_I2C3 0x1b8
145 #define CLK_SOURCE_SDMMC3 0x1bc
146 #define CLK_SOURCE_UARTD 0x1c0
147 #define CLK_SOURCE_VDE 0x1c8
148 #define CLK_SOURCE_OWR 0x1cc
149 #define CLK_SOURCE_NOR 0x1d0
150 #define CLK_SOURCE_CSITE 0x1d4
151 #define CLK_SOURCE_I2S0 0x1d8
152 #define CLK_SOURCE_DTV 0x1dc
153 #define CLK_SOURCE_MSENC 0x1f0
154 #define CLK_SOURCE_TSEC 0x1f4
155 #define CLK_SOURCE_SPARE2 0x1f8
157 #define CLK_OUT_ENB_X 0x280
158 #define RST_DEVICES_X 0x28C
160 #define RST_DEVICES_V 0x358
161 #define RST_DEVICES_W 0x35C
162 #define CLK_OUT_ENB_V 0x360
163 #define CLK_OUT_ENB_W 0x364
164 #define CCLKG_BURST_POLICY 0x368
165 #define SUPER_CCLKG_DIVIDER 0x36C
166 #define CCLKLP_BURST_POLICY 0x370
167 #define SUPER_CCLKLP_DIVIDER 0x374
169 #define CLK_SOURCE_MSELECT 0x3b4
170 #define CLK_SOURCE_TSENSOR 0x3b8
171 #define CLK_SOURCE_I2S3 0x3bc
172 #define CLK_SOURCE_I2S4 0x3c0
173 #define CLK_SOURCE_I2C4 0x3c4
174 #define CLK_SOURCE_SPI5 0x3c8
175 #define CLK_SOURCE_SPI6 0x3cc
176 #define CLK_SOURCE_AUDIO 0x3d0
177 #define CLK_SOURCE_DAM0 0x3d8
178 #define CLK_SOURCE_DAM1 0x3dc
179 #define CLK_SOURCE_DAM2 0x3e0
180 #define CLK_SOURCE_HDA2CODEC_2X 0x3e4
181 #define CLK_SOURCE_ACTMON 0x3e8
182 #define CLK_SOURCE_EXTPERIPH1 0x3ec
183 #define CLK_SOURCE_EXTPERIPH2 0x3f0
184 #define CLK_SOURCE_EXTPERIPH3 0x3f4
185 #define CLK_SOURCE_I2C_SLOW 0x3fc
187 #define CLK_SOURCE_SYS 0x400
188 #define CLK_SOURCE_SOR0 0x414
189 #define CLK_SOURCE_SATA_OOB 0x420
190 #define CLK_SOURCE_SATA 0x424
191 #define CLK_SOURCE_HDA 0x428
192 #define UTMIP_PLL_CFG0 0x480
193 #define UTMIP_PLL_CFG1 0x484
199 #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
200 #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
202 #define UTMIP_PLL_CFG2 0x488
203 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
204 #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
207 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
209 #define PLLE_AUX 0x48c
218 #define SATA_PLL_CFG0 0x490
227 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
229 #define SATA_PLL_CFG1 0x494
230 #define PCIE_PLL_CFG0 0x498
234 #define PLLD2_BASE 0x4b8
235 #define PLLD2_MISC 0x4bc
236 #define UTMIP_PLL_CFG3 0x4c0
237 #define PLLRE_BASE 0x4c4
238 #define PLLRE_MISC 0x4c8
239 #define PLLC2_BASE 0x4e8
240 #define PLLC2_MISC 0x4ec
241 #define PLLC3_BASE 0x4fc
243 #define PLLC3_MISC 0x500
244 #define PLLX_MISC2 0x514
245 #define PLLX_MISC2 0x514
246 #define PLLX_MISC3 0x518
247 #define PLLX_MISC3_DYNRAMP_STEPB_MASK 0xFF
249 #define PLLX_MISC3_DYNRAMP_STEPA_MASK 0xFF
251 #define PLLX_MISC3_NDIV_NEW_MASK 0xFF
258 #define PLLX_MISC3_EN_DYNRAMP (1 << 0)
259 #define XUSBIO_PLL_CFG0 0x51c
264 #define XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
266 #define PLLP_RESHIFT 0x528
267 #define UTMIPLL_HW_PWRDN_CFG0 0x52c
275 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL (1 << 0)
277 #define PLLDP_BASE 0x590
278 #define PLLDP_MISC 0x594
279 #define PLLC4_BASE 0x5a4
280 #define PLLC4_MISC 0x5a8
282 #define CLK_SOURCE_XUSB_CORE_HOST 0x600
283 #define CLK_SOURCE_XUSB_FALCON 0x604
284 #define CLK_SOURCE_XUSB_FS 0x608
285 #define CLK_SOURCE_XUSB_CORE_DEV 0x60c
286 #define CLK_SOURCE_XUSB_SS 0x610
287 #define CLK_SOURCE_CILAB 0x614
288 #define CLK_SOURCE_CILCD 0x618
289 #define CLK_SOURCE_CILE 0x61c
290 #define CLK_SOURCE_DSIA_LP 0x620
291 #define CLK_SOURCE_DSIB_LP 0x624
292 #define CLK_SOURCE_ENTROPY 0x628
293 #define CLK_SOURCE_DVFS_REF 0x62c
294 #define CLK_SOURCE_DVFS_SOC 0x630
295 #define CLK_SOURCE_TRACECLKIN 0x634
296 #define CLK_SOURCE_ADX 0x638
297 #define CLK_SOURCE_AMX 0x63c
298 #define CLK_SOURCE_EMC_LATENCY 0x640
299 #define CLK_SOURCE_SOC_THERM 0x644
300 #define CLK_SOURCE_VI_SENSOR2 0x658
301 #define CLK_SOURCE_I2C6 0x65c
302 #define CLK_SOURCE_EMC_DLL 0x664
303 #define CLK_SOURCE_HDMI_AUDIO 0x668
304 #define CLK_SOURCE_CLK72MHZ 0x66c
305 #define CLK_SOURCE_ADX1 0x670
306 #define CLK_SOURCE_AMX1 0x674
307 #define CLK_SOURCE_VIC 0x678
308 #define PLLP_OUTC 0x67c
309 #define PLLP_MISC1 0x680