Lines Matching +full:1 +full:x
8 * 1. Redistributions of source code must retain the above copyright
36 #define SOR_STATE0_UPDATE (1 << 0)
39 #define SOR_STATE1_ATTACHED (1 << 3)
40 #define SOR_STATE1_ASY_ORMODE_NORMAL (1 << 2)
41 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0) argument
43 #define ASY_HEAD_OPMODE_SNOOZE 1
47 #define SOR_STATE2_ASY_DEPOL_NEG (1 << 14)
48 #define SOR_STATE2_ASY_VSYNCPOL_NEG (1 << 13)
49 #define SOR_STATE2_ASY_HSYNCPOL_NEG (1 << 12)
50 #define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8) argument
51 #define ASY_PROTOCOL_SINGLE_TMDS_A 1
53 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6) argument
55 #define ASY_CRCMODE_COMPLETE 1
57 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4) argument
59 #define ASY_SUBOWNER_SUBHEAD0 1
62 #define SOR_STATE2_ASY_OWNER(x) (((x) & 0x3) << 0) argument
64 #define ASY_OWNER_HEAD0 1
67 #define AUDIO_INFOFRAME_CTRL_ENABLE (1 << 0)
72 #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) argument
73 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) argument
74 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) argument
77 #define AVI_INFOFRAME_CTRL_ENABLE (1 << 0)
86 #define GENERIC_CTRL_AUDIO (1 << 16)
87 #define GENERIC_CTRL_HBLANK (1 << 12)
88 #define GENERIC_CTRL_SINGLE (1 << 8)
89 #define GENERIC_CTRL_OTHER (1 << 4)
90 #define GENERIC_CTRL_ENABLE (1 << 0)
117 #define ACR_ENABLE (1U << 31)
118 #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8) argument
119 #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0) argument
122 #define HDMI_CTRL_ENABLE (1 << 30)
123 #define HDMI_CTRL_CA_SELECT (1 << 28)
124 #define HDMI_CTRL_SS_SELECT (1 << 27)
125 #define HDMI_CTRL_SF_SELECT (1 << 26)
126 #define HDMI_CTRL_CC_SELECT (1 << 25)
127 #define HDMI_CTRL_CT_SELECT (1 << 24)
128 #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16) argument
129 #define HDMI_CTRL_SAMPLE_FLAT (1 << 12)
130 #define HDMI_CTRL_AUDIO_LAYOUT_SELECT (1 << 10)
131 #define HDMI_CTRL_AUDIO_LAYOUT (1 << 8)
132 #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0) argument
135 #define VSYNC_WINDOW_ENABLE (1U << 31)
136 #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16) argument
137 #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0) argument
140 #define SPARE_ACR_PRIORITY (1U << 31)
141 #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16) argument
142 #define SPARE_SUPRESS_SP_B (1 << 2)
143 #define SPARE_FORCE_SW_CTS (1 << 1)
144 #define SPARE_HW_CTS (1 << 0)
147 #define SOR_PWR_SETTING_NEW (1U << 31)
148 #define SOR_PWR_SAFE_STATE_PU (1 << 16)
149 #define SOR_PWR_NORMAL_START_ALT (1 << 1)
150 #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
153 #define SOR_PLL0_TX_REG_LOAD(x) (((x) & 0xf) << 28) argument
154 #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24) argument
155 #define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16) argument
156 #define SOR_PLL0_BG_V17_S(x) (((x) & 0xf) << 12) argument
157 #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8) argument
158 #define SOR_PLL0_PULLDOWN (1 << 5)
159 #define SOR_PLL0_RESISTORSEL (1 << 4)
160 #define SOR_PLL0_PDPORT (1 << 3)
161 #define SOR_PLL0_VCOPD (1 << 2)
162 #define SOR_PLL0_PDBG (1 << 1)
163 #define SOR_PLL0_PWR (1 << 0)
166 #define SOR_PLL1_S_D_PIN_PE (1 << 30)
167 #define SOR_PLL1_HALF_FULL_PE (1 << 29)
168 #define SOR_PLL1_PE_EN (1 << 28)
169 #define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20) argument
170 #define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9) argument
171 #define SOR_PLL1_TMDS_TERM (1 << 8)
174 #define SOR_CSTM_ROTAT(x) (((x) & 0xf) << 28) argument
175 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) argument
176 #define SOR_CSTM_PLLDIV (1 << 21)
177 #define SOR_CSTM_BALANCED (1 << 19)
178 #define SOR_CSTM_NEW_MODE (1 << 18)
179 #define SOR_CSTM_DUP_SYNC (1 << 17)
180 #define SOR_CSTM_LVDS_ENABLE (1 << 16)
181 #define SOR_CSTM_LINKACTB (1 << 15)
182 #define SOR_CSTM_LINKACTA (1 << 14)
183 #define SOR_CSTM_MODE(x) (((x) & 0x3) << 12) argument
185 #define CSTM_MODE_TMDS 1
188 #define SOR_SEQ_SWITCH (1 << 30)
189 #define SOR_SEQ_STATUS (1 << 28)
190 #define SOR_SEQ_PC(x) (((x) & 0xf) << 16) argument
191 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12) argument
192 #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8) argument
193 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4) argument
194 #define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0) argument
196 #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x060 + (x)) argument
197 #define SOR_SEQ_INST_PLL_PULLDOWN (1U << 31)
198 #define SOR_SEQ_INST_POWERDOWN_MACRO (1 << 30)
199 #define SOR_SEQ_INST_ASSERT_PLL_RESETV (1 << 29)
200 #define SOR_SEQ_INST_BLANK_V (1 << 28)
201 #define SOR_SEQ_INST_BLANK_H (1 << 27)
202 #define SOR_SEQ_INST_BLANK_DE (1 << 26)
203 #define SOR_SEQ_INST_BLACK_DATA (1 << 25)
204 #define SOR_SEQ_INST_TRISTATE_IOS (1 << 24)
205 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
206 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
207 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
208 #define SOR_SEQ_INST_HALT (1 << 15)
209 #define SOR_SEQ_INST_WAIT_UNITS(x) (((x) & 0x3) << 12) argument
211 #define WAIT_UNITS_MS 1
213 #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0) argument
218 #define AUDIO_N_LOOKUP (1 << 28)
219 #define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
220 #define AUDIO_N_RESETF (1 << 20)
221 #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0) argument
224 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8) argument
225 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6) argument
228 #define ARM_VIDEO_RANGE_LIMITED (1 << 1)
229 #define HDMI_SRC_DISPLAYB (1 << 0)
233 #define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
234 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT(x) (((x) & 0x03) << 20) argument
236 #define SOURCE_SELECT_SPDIF 1
238 #define SOR_AUDIO_CNTRL0_AFIFO_FLUSH (1 << 12)
241 #define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27)
258 #define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1)
259 #define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)
271 #define INT_SCRATCH (1 << 3)
272 #define INT_CP_REQUEST (1 << 2)
273 #define INT_CODEC_SCRATCH1 (1 << 1)
274 #define INT_CODEC_SCRATCH0 (1 << 0)