1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
5  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
86 	struct mv_timer_config* config;  member
89 static struct resource_spec mv_timer_spec[] = {
92 	{ -1, 0 }
96 static struct ofw_compat_data mv_timer_compat[] = {
97 	{"marvell,armada-380-timer",	MV_NONE },
98 	{"marvell,armada-xp-timer",	MV_TMR | MV_WDT },
103 static struct mv_timer_softc *timer_softc = NULL;
104 static int timers_initialized = 0;
106 static int	mv_timer_probe(device_t);
107 static int	mv_timer_attach(device_t);
109 static int	mv_hardclock(void *);
110 static unsigned mv_timer_get_timecount(struct timecounter *);
112 static uint32_t	mv_get_timer_control(void);
113 static void	mv_set_timer_control(uint32_t);
114 static uint32_t	mv_get_timer(uint32_t);
115 static void	mv_set_timer(uint32_t, uint32_t);
116 static void	mv_set_timer_rel(uint32_t, uint32_t);
117 static void	mv_watchdog_event(void *, unsigned int, int *);
118 static int	mv_timer_start(struct eventtimer *et,
120 static int	mv_timer_stop(struct eventtimer *et);
121 static void	mv_setup_timers(void);
123 static void mv_watchdog_enable_armadaxp(void);
124 static void mv_watchdog_disable_armadaxp(void);
126 static void mv_delay(int usec, void* arg);
128 static struct mv_timer_config timer_armadaxp_config =
139 static struct ofw_compat_data mv_timer_soc_config[] = {
140 	{"marvell,armada-xp-timer",	(uintptr_t)&timer_armadaxp_config },
144 static struct timecounter mv_timer_timecounter = {
152 static int
159 	if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE)  in mv_timer_probe()
166 static int
180 	sc->config = (struct mv_timer_config*)  in mv_timer_attach()
181 	    ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data;  in mv_timer_attach()
183 	if (sc->config->clock_src == 0)  in mv_timer_attach()
184 		sc->config->clock_src = get_tclk();  in mv_timer_attach()
186 	error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res);  in mv_timer_attach()
192 	sc->timer_bst = rman_get_bustag(sc->timer_res[0]);  in mv_timer_attach()
193 	sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]);  in mv_timer_attach()
195 	sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt");  in mv_timer_attach()
197 	mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF);  in mv_timer_attach()
199 	if (sc->has_wdt) {  in mv_timer_attach()
200 		if (sc->config->watchdog_disable)  in mv_timer_attach()
201 			sc->config->watchdog_disable();  in mv_timer_attach()
205 	if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data  in mv_timer_attach()
207 		/* Don't set timers for wdt-only entry. */  in mv_timer_attach()
210 	} else if (sc->timer_res[1] == NULL) {  in mv_timer_attach()
212 		bus_release_resources(dev, mv_timer_spec, sc->timer_res);  in mv_timer_attach()
216 	if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK,  in mv_timer_attach()
218 		bus_release_resources(dev, mv_timer_spec, sc->timer_res);  in mv_timer_attach()
224 	if (sc->config->soc_family != MV_SOC_ARMADA_XP ) {  in mv_timer_attach()
225 		irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause);  in mv_timer_attach()
226 		irq_cause &= sc->config->irq_timer0_clr;  in mv_timer_attach()
228 		write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause);  in mv_timer_attach()
234 	sc->et.et_name = "CPUTimer0";  in mv_timer_attach()
235 	sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;  in mv_timer_attach()
236 	sc->et.et_quality = 1000;  in mv_timer_attach()
238 	sc->et.et_frequency = sc->config->clock_src;  in mv_timer_attach()
239 	sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;  in mv_timer_attach()
240 	sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;  in mv_timer_attach()
241 	sc->et.et_start = mv_timer_start;  in mv_timer_attach()
242 	sc->et.et_stop = mv_timer_stop;  in mv_timer_attach()
243 	sc->et.et_priv = sc;  in mv_timer_attach()
244 	et_register(&sc->et);  in mv_timer_attach()
245 	mv_timer_timecounter.tc_frequency = sc->config->clock_src;  in mv_timer_attach()
254 static int
260 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_hardclock()
261 	irq_cause &= timer_softc->config->irq_timer0_clr;  in mv_hardclock()
262 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_hardclock()
265 	if (sc->et.et_active)  in mv_hardclock()
266 		sc->et.et_event_cb(&sc->et, sc->et.et_arg);  in mv_hardclock()
271 static device_method_t mv_timer_methods[] = {
277 static driver_t mv_timer_driver = {
285 static unsigned
289 	return (INITIAL_TIMECOUNTER - mv_get_timer(1));  in mv_timer_get_timecount()
292 static void
299 	nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec);  in mv_delay()
304 			nticks -= (val - val_temp);  in mv_delay()
306 			nticks -= (val + (INITIAL_TIMECOUNTER - val_temp));  in mv_delay()
319 		for (; usec > 0; usec--)  in DELAY()
320 			for (val = 100; val > 0; val--)  in DELAY()
330 static uint32_t
334 	return (bus_space_read_4(timer_softc->timer_bst,  in mv_get_timer_control()
335 	    timer_softc->timer_bsh, CPU_TIMER_CONTROL));  in mv_get_timer_control()
338 static void
342 	bus_space_write_4(timer_softc->timer_bst,  in mv_set_timer_control()
343 	    timer_softc->timer_bsh, CPU_TIMER_CONTROL, val);  in mv_set_timer_control()
346 static uint32_t
350 	return (bus_space_read_4(timer_softc->timer_bst,  in mv_get_timer()
351 	    timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8));  in mv_get_timer()
354 static void
358 	bus_space_write_4(timer_softc->timer_bst,  in mv_set_timer()
359 	    timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val);  in mv_set_timer()
362 static void
366 	bus_space_write_4(timer_softc->timer_bst,  in mv_set_timer_rel()
367 	    timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val);  in mv_set_timer_rel()
370 static void
375 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_watchdog_enable_armadaxp()
376 	irq_cause &= timer_softc->config->irq_timer_wd_clr;  in mv_watchdog_enable_armadaxp()
377 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_watchdog_enable_armadaxp()
392 static void
405 	irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause);  in mv_watchdog_disable_armadaxp()
406 	irq_cause &= timer_softc->config->irq_timer_wd_clr;  in mv_watchdog_disable_armadaxp()
407 	write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause);  in mv_watchdog_disable_armadaxp()
417 static void
423 	mtx_lock(&timer_softc->timer_mtx);  in mv_watchdog_event()
425 		if (timer_softc->config->watchdog_disable != NULL)  in mv_watchdog_event()
426 			timer_softc->config->watchdog_disable();  in mv_watchdog_event()
433 		ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000;  in mv_watchdog_event()
435 			if (timer_softc->config->watchdog_disable != NULL)  in mv_watchdog_event()
436 				timer_softc->config->watchdog_disable();  in mv_watchdog_event()
439 			if (timer_softc->config->watchdog_enable != NULL)  in mv_watchdog_event()
440 				timer_softc->config->watchdog_enable();  in mv_watchdog_event()
444 	mtx_unlock(&timer_softc->timer_mtx);  in mv_watchdog_event()
447 static int
454 	sc = (struct mv_timer_softc *)et->et_priv;  in mv_timer_start()
456 		val = ((uint32_t)sc->et.et_frequency * period) >> 32;  in mv_timer_start()
460 		val1 = ((uint32_t)sc->et.et_frequency * first) >> 32;  in mv_timer_start()
477 static int
488 static void
499 	if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) {  in mv_setup_timers()