Lines Matching +full:pin +full:- +full:val
1 /*-
57 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
58 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
59 #define GPIO_LOCK_INIT(_sc) mtx_init(&_sc->mtx, \
60 device_get_nameunit(_sc->dev), "mvebu_gpio", MTX_DEF)
61 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx);
62 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED);
63 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED);
112 {"marvell,armada-8k-gpio", 1},
116 /* --------------------------------------------------------------------------
123 struct gpio_pin *pin, uint32_t val) in gpio_write() argument
127 bit = GPIO_BIT(pin->gp_pin); in gpio_write()
128 SYSCON_WRITE_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg, in gpio_write()
129 (val & 1) << bit); in gpio_write()
133 gpio_read(struct mvebu_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) in gpio_read() argument
136 uint32_t val; in gpio_read() local
138 bit = GPIO_BIT(pin->gp_pin); in gpio_read()
139 val = SYSCON_READ_4(sc->syscon, in gpio_read()
140 sc->offset + GPIO_REGNUM(pin->gp_pin) + reg); in gpio_read()
142 return (val >> bit) & 1; in gpio_read()
147 struct gpio_pin *pin, uint32_t val) in gpio_modify() argument
151 bit = GPIO_BIT(pin->gp_pin); in gpio_modify()
152 SYSCON_MODIFY_4(sc->syscon, sc->offset + GPIO_REGNUM(pin->gp_pin) + reg, in gpio_modify()
153 1 << bit, (val & 1) << bit); in gpio_modify()
157 mvebu_gpio_pin_configure(struct mvebu_gpio_softc *sc, struct gpio_pin *pin, in mvebu_gpio_pin_configure() argument
165 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); in mvebu_gpio_pin_configure()
167 pin->gp_flags |= GPIO_PIN_OUTPUT; in mvebu_gpio_pin_configure()
168 gpio_write(sc, GPIO_CONTROL_CLR, pin, 1); in mvebu_gpio_pin_configure()
170 pin->gp_flags |= GPIO_PIN_INPUT; in mvebu_gpio_pin_configure()
171 gpio_write(sc, GPIO_CONTROL_SET, pin, 1); in mvebu_gpio_pin_configure()
181 return (sc->busdev); in mvebu_gpio_get_bus()
190 *maxpin = sc->gpio_npins - 1; in mvebu_gpio_pin_max()
195 mvebu_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) in mvebu_gpio_pin_getcaps() argument
200 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_getcaps()
203 *caps = sc->gpio_pins[pin].gp_caps; in mvebu_gpio_pin_getcaps()
209 mvebu_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) in mvebu_gpio_pin_getflags() argument
214 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_getflags()
217 *flags = sc->gpio_pins[pin].gp_flags; in mvebu_gpio_pin_getflags()
223 mvebu_gpio_pin_getname(device_t dev, uint32_t pin, char *name) in mvebu_gpio_pin_getname() argument
228 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_getname()
231 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); in mvebu_gpio_pin_getname()
237 mvebu_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) in mvebu_gpio_pin_setflags() argument
242 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_setflags()
245 mvebu_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); in mvebu_gpio_pin_setflags()
251 mvebu_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) in mvebu_gpio_pin_set() argument
256 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_set()
260 gpio_write(sc, GPIO_DATA_SET, &sc->gpio_pins[pin], 1); in mvebu_gpio_pin_set()
262 gpio_write(sc, GPIO_DATA_CLR, &sc->gpio_pins[pin], 1); in mvebu_gpio_pin_set()
268 mvebu_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) in mvebu_gpio_pin_get() argument
273 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_get()
277 *val = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[pin]); in mvebu_gpio_pin_get()
278 *val ^= gpio_read(sc, GPIO_DATA_IN_POL, &sc->gpio_pins[pin]); in mvebu_gpio_pin_get()
285 mvebu_gpio_pin_toggle(device_t dev, uint32_t pin) in mvebu_gpio_pin_toggle() argument
288 uint32_t val; in mvebu_gpio_pin_toggle() local
291 if (pin >= sc->gpio_npins) in mvebu_gpio_pin_toggle()
295 mvebu_gpio_pin_get(sc->dev, pin, &val); in mvebu_gpio_pin_toggle()
296 if (val != 0) in mvebu_gpio_pin_toggle()
297 gpio_write(sc, GPIO_DATA_CLR, &sc->gpio_pins[pin], 1); in mvebu_gpio_pin_toggle()
299 gpio_write(sc, GPIO_DATA_SET, &sc->gpio_pins[pin], 1); in mvebu_gpio_pin_toggle()
305 /* --------------------------------------------------------------------------
312 struct mvebu_gpio_irqsrc *mgi, uint32_t val) in intr_modify() argument
316 bit = GPIO_BIT(mgi->irq); in intr_modify()
317 SYSCON_MODIFY_4(sc->syscon, in intr_modify()
318 sc->offset + GPIO_REGNUM(mgi->irq) + reg, 1 << bit, in intr_modify()
319 (val & 1) << bit); in intr_modify()
324 struct mvebu_gpio_irqsrc *mgi, uint32_t val) in mvebu_gpio_isrc_mask() argument
327 if (mgi->is_level) in mvebu_gpio_isrc_mask()
328 intr_modify(sc, GPIO_INT_LEVEL_MASK, mgi, val); in mvebu_gpio_isrc_mask()
330 intr_modify(sc, GPIO_INT_MASK, mgi, val); in mvebu_gpio_isrc_mask()
339 if (!mgi->is_level) { in mvebu_gpio_isrc_eoi()
340 bit = GPIO_BIT(mgi->irq); in mvebu_gpio_isrc_eoi()
341 SYSCON_WRITE_4(sc->syscon, in mvebu_gpio_isrc_eoi()
342 sc->offset + GPIO_REGNUM(mgi->irq) + GPIO_INT_CAUSE, in mvebu_gpio_isrc_eoi()
354 sc->isrcs = malloc(sizeof(*sc->isrcs) * sc->gpio_npins, M_DEVBUF, in mvebu_gpio_pic_attach()
357 name = device_get_nameunit(sc->dev); in mvebu_gpio_pic_attach()
358 for (irq = 0; irq < sc->gpio_npins; irq++) { in mvebu_gpio_pic_attach()
359 sc->isrcs[irq].irq = irq; in mvebu_gpio_pic_attach()
360 sc->isrcs[irq].is_level = false; in mvebu_gpio_pic_attach()
361 sc->isrcs[irq].is_inverted = false; in mvebu_gpio_pic_attach()
362 rv = intr_isrc_register(&sc->isrcs[irq].isrc, in mvebu_gpio_pic_attach()
363 sc->dev, 0, "%s,%u", name, irq); in mvebu_gpio_pic_attach()
367 if (intr_pic_register(sc->dev, in mvebu_gpio_pic_attach()
368 OF_xref_from_node(ofw_bus_get_node(sc->dev))) == NULL) in mvebu_gpio_pic_attach()
382 device_printf(sc->dev, "%s: not implemented yet\n", __func__); in mvebu_gpio_pic_detach()
418 * 1 = low-to-high edge triggered. in mvebu_gpio_pic_map_fdt()
419 * 2 = high-to-low edge triggered. in mvebu_gpio_pic_map_fdt()
420 * 4 = active high level-sensitive. in mvebu_gpio_pic_map_fdt()
421 * 8 = active low level-sensitive. in mvebu_gpio_pic_map_fdt()
423 if (ncells != 2 || cells[0] >= sc->gpio_npins) in mvebu_gpio_pic_map_fdt()
461 if (gpio_pin_num >= sc->gpio_npins) in mvebu_gpio_pic_map_gpio()
503 if (data->type == INTR_MAP_DATA_FDT) { in mvebu_gpio_pic_map_intr()
507 rv = mvebu_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, in mvebu_gpio_pic_map_intr()
509 } else if (data->type == INTR_MAP_DATA_GPIO) { in mvebu_gpio_pic_map_intr()
513 rv = mvebu_gpio_pic_map_gpio(sc, dag->gpio_pin_num, in mvebu_gpio_pic_map_intr()
514 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, NULL, NULL); in mvebu_gpio_pic_map_intr()
519 *isrcp = &sc->isrcs[irq].isrc; in mvebu_gpio_pic_map_intr()
531 if (mgi->is_level) in mvebu_gpio_pic_post_filter()
556 if (mgi->is_level) in mvebu_gpio_pic_pre_ithread()
577 if (data->type == INTR_MAP_DATA_FDT) { in mvebu_gpio_pic_setup_intr()
581 rv = mvebu_gpio_pic_map_fdt(sc, daf->ncells, daf->cells, &irq, in mvebu_gpio_pic_setup_intr()
583 } else if (data->type == INTR_MAP_DATA_GPIO) { in mvebu_gpio_pic_setup_intr()
587 rv = mvebu_gpio_pic_map_gpio(sc, dag->gpio_pin_num, in mvebu_gpio_pic_setup_intr()
588 dag->gpio_pin_flags, dag->gpio_intr_mode, &irq, in mvebu_gpio_pic_setup_intr()
600 if (isrc->isrc_handlers != 0) in mvebu_gpio_pic_setup_intr()
602 mgi->is_level == level && mgi->is_inverted == inverted ? in mvebu_gpio_pic_setup_intr()
605 mgi->is_level = level; in mvebu_gpio_pic_setup_intr()
606 mgi->is_inverted = inverted; in mvebu_gpio_pic_setup_intr()
626 if (isrc->isrc_handlers == 0) in mvebu_gpio_pic_teardown_intr()
631 /* --------------------------------------------------------------------------
647 sc = cookie->sc; in mvebu_gpio_intr()
648 tf = curthread->td_intr_frame; in mvebu_gpio_intr()
650 for (i = 0; i < sc->gpio_npins; i++) { in mvebu_gpio_intr()
651 lvl = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]); in mvebu_gpio_intr()
652 lvl &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]); in mvebu_gpio_intr()
653 edge = gpio_read(sc, GPIO_DATA_IN, &sc->gpio_pins[i]); in mvebu_gpio_intr()
654 edge &= gpio_read(sc, GPIO_INT_LEVEL_MASK, &sc->gpio_pins[i]); in mvebu_gpio_intr()
658 mgi = &sc->isrcs[i]; in mvebu_gpio_intr()
659 if (!mgi->is_level) in mvebu_gpio_intr()
662 if (intr_isrc_dispatch(&mgi->isrc, tf) != 0) { in mvebu_gpio_intr()
664 if (mgi->is_level) in mvebu_gpio_intr()
666 device_printf(sc->dev, in mvebu_gpio_intr()
667 "Stray irq %u disabled\n", mgi->irq); in mvebu_gpio_intr()
679 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in mvebu_gpio_probe()
694 KASSERT(mtx_initialized(&sc->mtx), ("gpio mutex not initialized")); in mvebu_gpio_detach()
697 if (sc->irq_ih[i] != NULL) in mvebu_gpio_detach()
698 bus_teardown_intr(dev, sc->irq_res[i], sc->irq_ih[i]); in mvebu_gpio_detach()
701 if (sc->isrcs != NULL) in mvebu_gpio_detach()
707 if (sc->irq_res[i] != NULL) in mvebu_gpio_detach()
709 sc->irq_res[i]); in mvebu_gpio_detach()
721 struct gpio_pin *pin; in mvebu_gpio_attach() local
726 sc->dev = dev; in mvebu_gpio_attach()
735 "ERROR: no pin-count or ngpios entry found!\n"); in mvebu_gpio_attach()
739 sc->gpio_npins = MIN(pincnt, MV_GPIO_MAX_NPINS); in mvebu_gpio_attach()
742 "%d pins available\n", sc->gpio_npins); in mvebu_gpio_attach()
744 rv = OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)); in mvebu_gpio_attach()
745 if (rv == -1) { in mvebu_gpio_attach()
750 if (SYSCON_GET_HANDLE(sc->dev, &sc->syscon) != 0 || in mvebu_gpio_attach()
751 sc->syscon == NULL) { in mvebu_gpio_attach()
758 sc->irq_cookies[i].sc = sc; in mvebu_gpio_attach()
759 sc->irq_cookies[i].bank_num = i; in mvebu_gpio_attach()
761 sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, in mvebu_gpio_attach()
763 if (sc->irq_res[i] == NULL) in mvebu_gpio_attach()
765 if ((bus_setup_intr(dev, sc->irq_res[i], in mvebu_gpio_attach()
767 &sc->irq_cookies[i], &sc->irq_ih[i]))) { in mvebu_gpio_attach()
776 for (i = 0; i < sc->gpio_npins; i++) { in mvebu_gpio_attach()
777 pin = sc->gpio_pins + i; in mvebu_gpio_attach()
778 pin->gp_pin = i; in mvebu_gpio_attach()
779 if (sc->irq_res[0] != NULL) in mvebu_gpio_attach()
780 pin->gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | in mvebu_gpio_attach()
784 pin->gp_caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; in mvebu_gpio_attach()
785 pin->gp_flags = in mvebu_gpio_attach()
786 gpio_read(sc, GPIO_CONTROL, &sc->gpio_pins[i]) == 0 ? in mvebu_gpio_attach()
788 snprintf(pin->gp_name, GPIOMAXNAME, "gpio%d", i); in mvebu_gpio_attach()
791 gpio_modify(sc, GPIO_INT_MASK, pin, 0); in mvebu_gpio_attach()
792 gpio_modify(sc, GPIO_INT_LEVEL_MASK, pin, 0); in mvebu_gpio_attach()
793 gpio_modify(sc, GPIO_INT_CAUSE, pin, 0); in mvebu_gpio_attach()
794 gpio_modify(sc, GPIO_DATA_IN_POL, pin, 0); in mvebu_gpio_attach()
795 gpio_modify(sc, GPIO_BLINK_ENA, pin, 0); in mvebu_gpio_attach()
798 if (sc->irq_res[0] != NULL) { in mvebu_gpio_attach()
807 sc->busdev = gpiobus_attach_bus(dev); in mvebu_gpio_attach()
808 if (sc->busdev == NULL) { in mvebu_gpio_attach()
818 int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) in mvebu_gpio_map_gpios() argument
823 *pin = gpios[0]; in mvebu_gpio_map_gpios()