Lines Matching +full:bus +full:- +full:addr
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 2010-2015 Semihalf
40 * Marvell integrated PCI/PCI-Express controller driver.
51 #include <sys/bus.h>
74 #include <machine/bus.h>
87 * Code and data related to fdt-based PCI configuration.
90 * always Marvell-specific so that was deleted and the code now lives here.
107 printf(" base_pci = 0x%08lx\n", range->base_pci); in mv_pci_range_dump()
108 printf(" base_par = 0x%08lx\n", range->base_parent); in mv_pci_range_dump()
109 printf(" len = 0x%08lx\n", range->len); in mv_pci_range_dump()
187 if ((par_addr_cells - offset_cells) > 2) { in mv_pci_ranges_decode()
191 pci_space->base_parent = fdt_data_get((void *)rangesptr, in mv_pci_ranges_decode()
192 par_addr_cells - offset_cells); in mv_pci_ranges_decode()
193 rangesptr += par_addr_cells - offset_cells; in mv_pci_ranges_decode()
199 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); in mv_pci_ranges_decode()
202 pci_space->base_pci = cell2; in mv_pci_ranges_decode()
204 if (pci_space->len == 0) { in mv_pci_ranges_decode()
205 pci_space->len = PCI_SPACE_LEN; in mv_pci_ranges_decode()
206 pci_space->base_parent = fdt_immr_va + in mv_pci_ranges_decode()
243 devmap->pd_va = (io_va ? io_va : io_space.base_parent); in mv_pci_devmap()
244 devmap->pd_pa = io_space.base_parent; in mv_pci_devmap()
245 devmap->pd_size = io_space.len; in mv_pci_devmap()
248 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); in mv_pci_devmap()
249 devmap->pd_pa = mem_space.base_parent; in mv_pci_devmap()
250 devmap->pd_size = mem_space.len; in mv_pci_devmap()
259 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) argument
314 int sc_busnr; /* Host bridge bus number */
371 * Bus interface definitions.
378 /* Bus interface */
403 /* OFW bus interface */
436 OF_parent(node), "marvell,armada-370-pcie"))) in mv_pcib_probe()
442 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); in mv_pcib_probe()
452 int err, bus, devfn, port_id; in mv_pcib_attach() local
455 sc->sc_dev = self; in mv_pcib_attach()
460 if (OF_getencprop(node, "marvell,pcie-port", &(port_id), in mv_pcib_attach()
463 if (!OF_hasprop(node, "marvell,pcie-port")) in mv_pcib_attach()
469 sc->ap_segment = port_id; in mv_pcib_attach()
472 sc->sc_type = MV_TYPE_PCIE; in mv_pcib_attach()
473 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id); in mv_pcib_attach()
474 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id); in mv_pcib_attach()
475 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id); in mv_pcib_attach()
476 sc->sc_skip_enable_procedure = 1; in mv_pcib_attach()
477 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) { in mv_pcib_attach()
478 sc->sc_type = MV_TYPE_PCIE; in mv_pcib_attach()
479 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id); in mv_pcib_attach()
480 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id); in mv_pcib_attach()
481 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id); in mv_pcib_attach()
482 sc->sc_enable_find_root_slot = 1; in mv_pcib_attach()
484 sc->sc_type = MV_TYPE_PCI; in mv_pcib_attach()
485 sc->sc_win_target = MV_WIN_PCI_TARGET; in mv_pcib_attach()
486 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; in mv_pcib_attach()
487 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; in mv_pcib_attach()
492 * Retrieve our mem-mapped registers range. in mv_pcib_attach()
494 sc->sc_rid = 0; in mv_pcib_attach()
495 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, in mv_pcib_attach()
497 if (sc->sc_res == NULL) { in mv_pcib_attach()
501 sc->sc_bst = rman_get_bustag(sc->sc_res); in mv_pcib_attach()
502 sc->sc_bsh = rman_get_bushandle(sc->sc_res); in mv_pcib_attach()
504 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); in mv_pcib_attach()
505 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : in mv_pcib_attach()
511 if (sc->sc_mode == MV_MODE_ROOT) in mv_pcib_attach()
512 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); in mv_pcib_attach()
535 * Preliminary bus enumeration to find first linked devices and set in mv_pcib_attach()
536 * appropriate bus number from which should start the actual enumeration in mv_pcib_attach()
538 for (bus = 0; bus < PCI_BUSMAX; bus++) { in mv_pcib_attach()
540 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4); in mv_pcib_attach()
544 sc->sc_busnr = bus; /* update bus number */ in mv_pcib_attach()
550 if (sc->sc_mode == MV_MODE_ROOT) { in mv_pcib_attach()
551 err = mv_pcib_init(sc, sc->sc_busnr, in mv_pcib_attach()
552 mv_pcib_maxslots(sc->sc_dev)); in mv_pcib_attach()
558 sc->sc_devnr = 1; in mv_pcib_attach()
559 bus_space_write_4(sc->sc_bst, sc->sc_bsh, in mv_pcib_attach()
564 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); in mv_pcib_attach()
570 rman_fini(&sc->sc_mem_rman); in mv_pcib_attach()
571 rman_fini(&sc->sc_io_rman); in mv_pcib_attach()
582 if (sc->sc_skip_enable_procedure) in mv_pcib_enable()
588 if ((sc->sc_skip_enable_procedure == 0) && in mv_pcib_enable()
594 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, in mv_pcib_enable()
598 timeout -= 1000; in mv_pcib_enable()
599 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, in mv_pcib_enable()
605 if (sc->sc_mode == MV_MODE_ROOT) { in mv_pcib_enable()
609 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); in mv_pcib_enable()
612 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); in mv_pcib_enable()
624 sc->sc_mem_rman.rm_type = RMAN_ARRAY; in mv_pcib_mem_init()
625 err = rman_init(&sc->sc_mem_rman); in mv_pcib_mem_init()
629 sc->sc_io_rman.rm_type = RMAN_ARRAY; in mv_pcib_mem_init()
630 err = rman_init(&sc->sc_io_rman); in mv_pcib_mem_init()
632 rman_fini(&sc->sc_mem_rman); in mv_pcib_mem_init()
636 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, in mv_pcib_mem_init()
637 sc->sc_mem_base + sc->sc_mem_size - 1); in mv_pcib_mem_init()
641 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, in mv_pcib_mem_init()
642 sc->sc_io_base + sc->sc_io_size - 1); in mv_pcib_mem_init()
649 rman_fini(&sc->sc_mem_rman); in mv_pcib_mem_init()
650 rman_fini(&sc->sc_io_rman); in mv_pcib_mem_init()
695 * The idea of this allocator is taken from ARM No-Cache memory
702 bus_addr_t addr = 0; in pcib_alloc() local
706 base = sc->sc_io_base; in pcib_alloc()
708 bits_limit = sc->sc_io_size / min_alloc; in pcib_alloc()
709 map = sc->sc_io_map; in pcib_alloc()
712 base = sc->sc_mem_base; in pcib_alloc()
714 bits_limit = sc->sc_mem_size / min_alloc; in pcib_alloc()
715 map = sc->sc_mem_map; in pcib_alloc()
725 addr = base + (i * min_alloc); in pcib_alloc()
726 return (addr); in pcib_alloc()
729 return (addr); in pcib_alloc()
733 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, in mv_pcib_init_bar() argument
736 uint32_t addr, bar; in mv_pcib_init_bar() local
745 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); in mv_pcib_init_bar()
746 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); in mv_pcib_init_bar()
750 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ in mv_pcib_init_bar()
753 addr = pcib_alloc(sc, bar); in mv_pcib_init_bar()
754 if (!addr) in mv_pcib_init_bar()
755 return (-1); in mv_pcib_init_bar()
758 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", in mv_pcib_init_bar()
759 bus, slot, func, reg, bar, addr); in mv_pcib_init_bar()
761 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); in mv_pcib_init_bar()
763 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, in mv_pcib_init_bar()
770 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) in mv_pcib_init_bridge() argument
776 io_base = sc->sc_io_base; in mv_pcib_init_bridge()
777 io_limit = io_base + sc->sc_io_size - 1; in mv_pcib_init_bridge()
778 mem_base = sc->sc_mem_base; in mv_pcib_init_bridge()
779 mem_limit = mem_base + sc->sc_mem_size - 1; in mv_pcib_init_bridge()
782 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, in mv_pcib_init_bridge()
784 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, in mv_pcib_init_bridge()
786 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, in mv_pcib_init_bridge()
788 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, in mv_pcib_init_bridge()
792 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, in mv_pcib_init_bridge()
794 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, in mv_pcib_init_bridge()
798 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, in mv_pcib_init_bridge()
800 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, in mv_pcib_init_bridge()
802 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, in mv_pcib_init_bridge()
804 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, in mv_pcib_init_bridge()
807 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, in mv_pcib_init_bridge()
815 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) in mv_pcib_init() argument
823 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, in mv_pcib_init()
832 command = mv_pcib_read_config(sc->sc_dev, bus, slot, in mv_pcib_init()
835 mv_pcib_write_config(sc->sc_dev, bus, slot, func, in mv_pcib_init()
838 error = mv_pcib_init_all_bars(sc, bus, slot, func, in mv_pcib_init()
846 mv_pcib_write_config(sc->sc_dev, bus, slot, func, in mv_pcib_init()
849 /* Handle PCI-PCI bridges */ in mv_pcib_init()
850 class = mv_pcib_read_config(sc->sc_dev, bus, slot, in mv_pcib_init()
852 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, in mv_pcib_init()
859 mv_pcib_init_bridge(sc, bus, slot, func); in mv_pcib_init()
870 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, in mv_pcib_init_all_bars() argument
880 i = mv_pcib_init_bar(sc, bus, slot, func, bar); in mv_pcib_init_all_bars()
883 device_printf(sc->sc_dev, in mv_pcib_init_all_bars()
899 return (&sc->sc_io_rman); in mv_pcib_get_rman()
901 return (&sc->sc_mem_rman); in mv_pcib_get_rman()
918 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start, in mv_pcib_alloc_resource()
926 start = sc->sc_mem_base; in mv_pcib_alloc_resource()
927 end = sc->sc_mem_base + sc->sc_mem_size - 1; in mv_pcib_alloc_resource()
928 count = sc->sc_mem_size; in mv_pcib_alloc_resource()
931 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || in mv_pcib_alloc_resource()
932 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) in mv_pcib_alloc_resource()
951 return (pci_domain_adjust_bus(sc->ap_segment, child, r, start, in mv_pcib_adjust_resource()
968 return (pci_domain_release_bus(sc->ap_segment, child, res)); in mv_pcib_release_resource()
984 return (pci_domain_activate_bus(sc->ap_segment, child, r)); in mv_pcib_activate_resource()
1000 return (pci_domain_deactivate_bus(sc->ap_segment, child, r)); in mv_pcib_deactivate_resource()
1032 map->r_bustag = fdtbus_bs_tag; in mv_pcib_map_resource()
1033 map->r_bushandle = start; in mv_pcib_map_resource()
1034 map->r_size = length; in mv_pcib_map_resource()
1058 *result = sc->sc_busnr; in mv_pcib_read_ivar()
1075 sc->sc_busnr = value; in mv_pcib_write_ivar()
1086 if (sc->sc_type != MV_TYPE_PCIE) in pcib_write_irq_mask()
1089 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); in pcib_write_irq_mask()
1105 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, in mv_pcib_hw_cfgread() argument
1108 uint32_t addr, data, ca, cd; in mv_pcib_hw_cfgread() local
1110 ca = (sc->sc_type != MV_TYPE_PCI) ? in mv_pcib_hw_cfgread()
1112 cd = (sc->sc_type != MV_TYPE_PCI) ? in mv_pcib_hw_cfgread()
1114 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | in mv_pcib_hw_cfgread()
1118 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); in mv_pcib_hw_cfgread()
1123 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, in mv_pcib_hw_cfgread()
1127 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, in mv_pcib_hw_cfgread()
1131 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, in mv_pcib_hw_cfgread()
1140 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, in mv_pcib_hw_cfgwrite() argument
1143 uint32_t addr, ca, cd; in mv_pcib_hw_cfgwrite() local
1145 ca = (sc->sc_type != MV_TYPE_PCI) ? in mv_pcib_hw_cfgwrite()
1147 cd = (sc->sc_type != MV_TYPE_PCI) ? in mv_pcib_hw_cfgwrite()
1149 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | in mv_pcib_hw_cfgwrite()
1153 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); in mv_pcib_hw_cfgwrite()
1157 bus_space_write_1(sc->sc_bst, sc->sc_bsh, in mv_pcib_hw_cfgwrite()
1161 bus_space_write_2(sc->sc_bst, sc->sc_bsh, in mv_pcib_hw_cfgwrite()
1165 bus_space_write_4(sc->sc_bst, sc->sc_bsh, in mv_pcib_hw_cfgwrite()
1177 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); in mv_pcib_maxslots()
1181 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) in mv_pcib_root_slot() argument
1187 if (!sc->sc_enable_find_root_slot) in mv_pcib_root_slot()
1190 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, in mv_pcib_root_slot()
1192 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, in mv_pcib_root_slot()
1199 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, in mv_pcib_read_config() argument
1205 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & in mv_pcib_read_config()
1206 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) in mv_pcib_read_config()
1209 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); in mv_pcib_read_config()
1213 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, in mv_pcib_write_config() argument
1219 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & in mv_pcib_write_config()
1220 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) in mv_pcib_write_config()
1223 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); in mv_pcib_write_config()
1227 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) in mv_pcib_route_interrupt() argument
1235 sc = device_get_softc(bus); in mv_pcib_route_interrupt()
1244 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, in mv_pcib_route_interrupt()
1254 device_printf(bus, "could not route pin %d for device %d.%d\n", in mv_pcib_route_interrupt()
1266 dev = sc->sc_dev; in mv_pcib_decode_win()
1274 error = decode_win_cpu_set(sc->sc_win_target, in mv_pcib_decode_win()
1275 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); in mv_pcib_decode_win()
1281 error = decode_win_cpu_set(sc->sc_win_target, in mv_pcib_decode_win()
1282 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, in mv_pcib_decode_win()
1290 sc->sc_io_base = io_space.base_parent; in mv_pcib_decode_win()
1291 sc->sc_io_size = io_space.len; in mv_pcib_decode_win()
1293 sc->sc_mem_base = mem_space.base_parent; in mv_pcib_decode_win()
1294 sc->sc_mem_size = mem_space.len; in mv_pcib_decode_win()
1300 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, in mv_pcib_map_msi() argument
1306 if (!sc->sc_msi_supported) in mv_pcib_map_msi()
1309 irq = irq - MSI_IRQ; in mv_pcib_map_msi()
1312 if (isclr(&sc->sc_msi_bitmap, irq)) { in mv_pcib_map_msi()
1317 mv_msi_data(irq, addr, data); in mv_pcib_map_msi()
1319 debugf("%s: irq: %d addr: %jx data: %x\n", in mv_pcib_map_msi()
1320 __func__, irq, *addr, *data); in mv_pcib_map_msi()
1333 if (!sc->sc_msi_supported) in mv_pcib_alloc_msi()
1339 mtx_lock(&sc->sc_msi_mtx); in mv_pcib_alloc_msi()
1343 if (isset(&sc->sc_msi_bitmap, i)) in mv_pcib_alloc_msi()
1351 mtx_unlock(&sc->sc_msi_mtx); in mv_pcib_alloc_msi()
1356 setbit(&sc->sc_msi_bitmap, i); in mv_pcib_alloc_msi()
1361 mtx_unlock(&sc->sc_msi_mtx); in mv_pcib_alloc_msi()
1372 if(!sc->sc_msi_supported) in mv_pcib_release_msi()
1375 mtx_lock(&sc->sc_msi_mtx); in mv_pcib_release_msi()
1378 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); in mv_pcib_release_msi()
1380 mtx_unlock(&sc->sc_msi_mtx); in mv_pcib_release_msi()