1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
4  * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
187 	{ "marvell,armada-370-neta", &decode_win_neta_setup,
189 	{ "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid},
190 	{ "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid },
191 	{ "marvell,armada-380-xhci", &decode_win_usb3_setup,
193 	{ "marvell,armada-380-ahci", &decode_win_ahci_setup,
195 	{ "marvell,armada-380-sdhci", &decode_win_sdhci_setup,
202 	{ "marvell,armada-38x-crypto", &decode_win_a38x_cesa_setup,
294 	{ "mrvl,usb-ehci",	CPU_PM_CTRL_USB(0) },
295 	{ "mrvl,usb-ehci",	CPU_PM_CTRL_USB(1) },
296 	{ "mrvl,usb-ehci",	CPU_PM_CTRL_USB(2) },
304  * 1 - Device Power On
305  * 0 - Device Power Off
308  * loader> set hw.pm-disable-mask=0x2
311  * |-------------------------------|
313  * |-------------------------------|
315  * |-------------------------------|
316  * | USB1   |     -    | 0x040000  |
317  * |-------------------------------|
318  * | USB2   |     -    | 0x080000  |
319  * |-------------------------------|
321  * |-------------------------------|
322  * | GE1    |     -    | 0x000004  |
323  * |-------------------------------|
324  * | IDMA   |     -    | 0x100000  |
325  * |-------------------------------|
327  * |-------------------------------|
329  * |-------------------------------|
331  * --------------------------------|
441 	if (soc_decode_win_spec->read_cpu_ctrl != NULL)  in read_cpu_ctrl()
442 		return (soc_decode_win_spec->read_cpu_ctrl(reg));  in read_cpu_ctrl()
443 	return (-1);  in read_cpu_ctrl()
457 	if (soc_decode_win_spec->write_cpu_ctrl != NULL)  in write_cpu_ctrl()
458 		soc_decode_win_spec->write_cpu_ctrl(reg, val);  in write_cpu_ctrl()
522 	if ((node = OF_finddevice("/")) == -1)  in soc_id()
597 	TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask);  in soc_decode_win()
642 	if (soc_decode_win_spec->cr_read != NULL)  in WIN_REG_IDX_RD()
643 		return (soc_decode_win_spec->cr_read(i));  in WIN_REG_IDX_RD()
644 	return (-1);  in WIN_REG_IDX_RD()
651 	if (soc_decode_win_spec->br_read != NULL)  in win_cpu_br_read()
652 		return (soc_decode_win_spec->br_read(i));  in win_cpu_br_read()
653 	return (-1);  in win_cpu_br_read()
660 	if (soc_decode_win_spec->remap_l_read != NULL)  in win_cpu_remap_l_read()
661 		return (soc_decode_win_spec->remap_l_read(i));  in win_cpu_remap_l_read()
662 	return (-1);  in win_cpu_remap_l_read()
669 	if (soc_decode_win_spec->remap_h_read != NULL)  in win_cpu_remap_h_read()
670 		return soc_decode_win_spec->remap_h_read(i);  in win_cpu_remap_h_read()
671 	return (-1);  in win_cpu_remap_h_read()
678 	if (soc_decode_win_spec->cr_write != NULL)  in win_cpu_cr_write()
679 		soc_decode_win_spec->cr_write(i, val);  in win_cpu_cr_write()
686 	if (soc_decode_win_spec->br_write != NULL)  in win_cpu_br_write()
687 		soc_decode_win_spec->br_write(i, val);  in win_cpu_br_write()
694 	if (soc_decode_win_spec->remap_l_write != NULL)  in win_cpu_remap_l_write()
695 		soc_decode_win_spec->remap_l_write(i, val);  in win_cpu_remap_l_write()
702 	if (soc_decode_win_spec->remap_h_write != NULL)  in win_cpu_remap_h_write()
703 		soc_decode_win_spec->remap_h_write(i, val);  in win_cpu_remap_h_write()
772 	if (soc_decode_win_spec->ddr_br_read != NULL)  in WIN_REG_IDX_RD()
773 		return (soc_decode_win_spec->ddr_br_read(i));  in WIN_REG_IDX_RD()
774 	return (-1);  in WIN_REG_IDX_RD()
781 	if (soc_decode_win_spec->ddr_sz_read != NULL)  in ddr_sz_read()
782 		return (soc_decode_win_spec->ddr_sz_read(i));  in ddr_sz_read()
783 	return (-1);  in ddr_sz_read()
790 	if (soc_decode_win_spec->ddr_br_write != NULL)  in ddr_br_write()
791 		soc_decode_win_spec->ddr_br_write(i, val);  in ddr_br_write()
798 	if (soc_decode_win_spec->ddr_sz_write != NULL)  in ddr_sz_write()
799 		soc_decode_win_spec->ddr_sz_write(i, val);  in ddr_sz_write()
803  * On 88F6781 (Dove) SoC DDR Controller is accessed through
804  * single MBUS <-> AXI bridge. In this case we provide emulated
831 	return (((size - 1) << 16) | (mmap & 0x01));  in ddr_sz_read()
843 	for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) {  in soc_dump_decode_win()
896 		if ((tab->base + tab->size - 1) < (wintab + win)->base)  in decode_win_overlap()
899 		else if (((wintab + win)->base + (wintab + win)->size - 1) <  in decode_win_overlap()
900 		    tab->base)  in decode_win_overlap()
906 	return (-1);  in decode_win_overlap()
917 		win = soc_decode_win_spec->mv_win_cpu_max - 1;  in decode_win_cpu_set()
918 		i = -1;  in decode_win_cpu_set()
924 	while ((win >= 0) && (win < soc_decode_win_spec->mv_win_cpu_max)) {  in decode_win_cpu_set()
935 	if ((win < 0) || (win >= soc_decode_win_spec->mv_win_cpu_max) ||  in decode_win_cpu_set()
937 		return (-1);  in decode_win_cpu_set()
949 			 * (capable of remapping) - set remap field with the  in decode_win_cpu_set()
957 	cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |  in decode_win_cpu_set()
970 	for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) {  in decode_win_cpu_setup()
1003 	/* Try to match entries from device tree with settings from u-boot */  in decode_win_sdram_fixup()
1153 			cr = (((size - 1) & 0xffff0000) |  in decode_win_cesa_setup()
1228 			cr = (((ddr_size(i) - 1) & 0xffff0000) |  in decode_win_usb_setup()
1282 			cr = (((ddr_size(i) - 1) &  in decode_win_usb3_setup()
1308 	/* ETH encode windows 0-3 have remap capability */  in win_eth_can_remap()
1391 			sz = ((ddr_size(i) - 1) & 0xffff0000);  in decode_win_eth_setup()
1476 	/* On End-Point only set BAR size to 1MB regardless of DDR size */  in decode_win_pcie_setup()
1486 			cr = (ddr_size(i) - 1) & 0xffff0000;  in decode_win_pcie_setup()
1510 	size -= 0x10000;  in decode_win_pcie_setup()
1584 			cr = ((ddr_size(i) - 1) & 0xffff0000) |  in decode_win_sata_setup()
1620 			sz = (ddr_size(i) - 1) &  in decode_win_ahci_setup()
1632 				/* SIZE is set to 16MB - max value */  in decode_win_ahci_setup()
1675 			cr = (((ddr_size(i) - 1) &  in decode_win_sdhci_setup()
1680 			/* Use the first available SDHCI window */  in decode_win_sdhci_setup()
1698 		printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i,  in decode_win_sdhci_dump()
1722 	if (node == -1)  in fdt_get_ranges()
1797 	if ((node = OF_finddevice("sram")) != -1)  in win_cpu_from_dt()
1798 		if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram"))  in win_cpu_from_dt()
1801 	if ((node = OF_finddevice("/")) == -1)  in win_cpu_from_dt()
1804 	if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)  in win_cpu_from_dt()
1818 	cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target;  in win_cpu_from_dt()
1820 		cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(0);  in win_cpu_from_dt()
1822 		cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1);  in win_cpu_from_dt()
1831 		if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) {  in win_cpu_from_dt()
1848 	cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target;  in win_cpu_from_dt()
1849 	cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1);  in win_cpu_from_dt()
1900 		base = fdt_data_get(&reg[addr_cells - 2], 2);  in fdt_win_process_child()
1903 	if (soc_node->valid_handler != NULL)  in fdt_win_process_child()
1904 		if (!soc_node->valid_handler())  in fdt_win_process_child()
1908 	if (soc_node->decode_handler != NULL)  in fdt_win_process_child()
1909 		soc_node->decode_handler(base);  in fdt_win_process_child()
1913 	if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))  in fdt_win_process_child()
1914 		soc_node->dump_handler(base);  in fdt_win_process_child()
1928 	if (node == -1)  in fdt_win_setup()
1936 	 * Traverse through all children of root and simple-bus nodes.  in fdt_win_setup()
1946 		/* Process Marvell Armada-XP/38x PCIe controllers */  in fdt_win_setup()
1947 		if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) {  in fdt_win_setup()
1952 				    "assigned-addresses");  in fdt_win_setup()
1961 		 * Once done with root-level children let's move down to  in fdt_win_setup()
1962 		 * simple-bus and its children.  in fdt_win_setup()
1966 			sb = node = fdt_find_compatible(node, "simple-bus", 0);  in fdt_win_setup()
1972 		 * Next, move one more level down to internal-regs node (if  in fdt_win_setup()
1974 		 * "simple-bus" compatible.  in fdt_win_setup()
1977 			node = fdt_find_compatible(node, "simple-bus", 0);  in fdt_win_setup()
1998 	if ((sb = OF_finddevice("cpu")) != -1)  in fdt_fixup_busfreq()
2000 			OF_setprop(sb, "bus-frequency", (void *)&freq,  in fdt_fixup_busfreq()
2004 	 * This fixup sets the simple-bus bus-frequency property.  in fdt_fixup_busfreq()
2006 	if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)  in fdt_fixup_busfreq()
2007 		OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));  in fdt_fixup_busfreq()
2019 	/* Fix-up SoC ranges according to real fdt_immr_pa */  in fdt_fixup_ranges()
2020 	if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {  in fdt_fixup_ranges()
2042 	/* Fix-up PCIe reg according to real PCIe registers' PA */  in fdt_fixup_ranges()
2063 	/* Fix-up succeeded. May return and continue */  in fdt_fixup_ranges()
2080 	{ "mrvl,DB-88F6281", &fdt_fixup_busfreq },
2081 	{ "mrvl,DB-78460", &fdt_fixup_busfreq },
2082 	{ "mrvl,DB-78460", &fdt_fixup_ranges },
2090 	if (soc_decode_win_spec->get_tclk != NULL)  in get_tclk()
2091 		return soc_decode_win_spec->get_tclk();  in get_tclk()
2093 		return -1;  in get_tclk()
2100 	if (soc_decode_win_spec->get_cpu_freq != NULL)  in get_cpu_freq()
2101 		return soc_decode_win_spec->get_cpu_freq();  in get_cpu_freq()
2103 		return -1;  in get_cpu_freq()