Lines Matching +full:armada +full:- +full:xp +full:- +full:sdram +full:- +full:controller
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
212 { "marvell,armada-370-neta", &decode_win_neta_setup,
214 { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid},
215 { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid },
216 { "marvell,armada-380-xhci", &decode_win_usb3_setup,
218 { "marvell,armada-380-ahci", &decode_win_ahci_setup,
220 { "marvell,armada-380-sdhci", &decode_win_sdhci_setup,
227 { "marvell,armada-38x-crypto", &decode_win_a38x_cesa_setup,
340 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) },
341 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) },
342 { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) },
360 * 1 - Device Power On
361 * 0 - Device Power Off
364 * loader> set hw.pm-disable-mask=0x2
367 * |-------------------------------|
369 * |-------------------------------|
371 * |-------------------------------|
372 * | USB1 | - | 0x040000 |
373 * |-------------------------------|
374 * | USB2 | - | 0x080000 |
375 * |-------------------------------|
377 * |-------------------------------|
378 * | GE1 | - | 0x000004 |
379 * |-------------------------------|
380 * | IDMA | - | 0x100000 |
381 * |-------------------------------|
383 * |-------------------------------|
385 * |-------------------------------|
387 * --------------------------------|
534 if (soc_decode_win_spec->read_cpu_ctrl != NULL) in read_cpu_ctrl()
535 return (soc_decode_win_spec->read_cpu_ctrl(reg)); in read_cpu_ctrl()
536 return (-1); in read_cpu_ctrl()
557 if (soc_decode_win_spec->write_cpu_ctrl != NULL) in write_cpu_ctrl()
558 soc_decode_win_spec->write_cpu_ctrl(reg, val); in write_cpu_ctrl()
671 * PCIE controller, so using this function is only allowed (and in soc_id()
677 if ((node = OF_finddevice("/")) == -1) in soc_id()
795 printf(" 256KB 4-way set-associative %s unified L2 cache\n", in soc_identify()
796 mode ? "write-through" : "write-back"); in soc_identify()
802 printf(" %s set-associative %s unified L2 cache\n", in soc_identify()
803 size ? "256KB 4-way" : "512KB 8-way", in soc_identify()
804 mode ? "write-through" : "write-back"); in soc_identify()
829 TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); in soc_decode_win()
882 if (soc_decode_win_spec->cr_read != NULL) in WIN_REG_IDX_RD()
883 return (soc_decode_win_spec->cr_read(i)); in WIN_REG_IDX_RD()
884 return (-1); in WIN_REG_IDX_RD()
891 if (soc_decode_win_spec->br_read != NULL) in win_cpu_br_read()
892 return (soc_decode_win_spec->br_read(i)); in win_cpu_br_read()
893 return (-1); in win_cpu_br_read()
900 if (soc_decode_win_spec->remap_l_read != NULL) in win_cpu_remap_l_read()
901 return (soc_decode_win_spec->remap_l_read(i)); in win_cpu_remap_l_read()
902 return (-1); in win_cpu_remap_l_read()
909 if (soc_decode_win_spec->remap_h_read != NULL) in win_cpu_remap_h_read()
910 return soc_decode_win_spec->remap_h_read(i); in win_cpu_remap_h_read()
911 return (-1); in win_cpu_remap_h_read()
918 if (soc_decode_win_spec->cr_write != NULL) in win_cpu_cr_write()
919 soc_decode_win_spec->cr_write(i, val); in win_cpu_cr_write()
926 if (soc_decode_win_spec->br_write != NULL) in win_cpu_br_write()
927 soc_decode_win_spec->br_write(i, val); in win_cpu_br_write()
934 if (soc_decode_win_spec->remap_l_write != NULL) in win_cpu_remap_l_write()
935 soc_decode_win_spec->remap_l_write(i, val); in win_cpu_remap_l_write()
942 if (soc_decode_win_spec->remap_h_write != NULL) in win_cpu_remap_h_write()
943 soc_decode_win_spec->remap_h_write(i, val); in win_cpu_remap_h_write()
1017 if (soc_decode_win_spec->ddr_br_read != NULL) in WIN_REG_IDX_RD()
1018 return (soc_decode_win_spec->ddr_br_read(i)); in WIN_REG_IDX_RD()
1019 return (-1); in WIN_REG_IDX_RD()
1026 if (soc_decode_win_spec->ddr_sz_read != NULL) in ddr_sz_read()
1027 return (soc_decode_win_spec->ddr_sz_read(i)); in ddr_sz_read()
1028 return (-1); in ddr_sz_read()
1035 if (soc_decode_win_spec->ddr_br_write != NULL) in ddr_br_write()
1036 soc_decode_win_spec->ddr_br_write(i, val); in ddr_br_write()
1043 if (soc_decode_win_spec->ddr_sz_write != NULL) in ddr_sz_write()
1044 soc_decode_win_spec->ddr_sz_write(i, val); in ddr_sz_write()
1048 * On 88F6781 (Dove) SoC DDR Controller is accessed through
1049 * single MBUS <-> AXI bridge. In this case we provide emulated
1076 return (((size - 1) << 16) | (mmap & 0x01)); in ddr_sz_read()
1088 for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) { in soc_dump_decode_win()
1149 if ((tab->base + tab->size - 1) < (wintab + win)->base) in decode_win_overlap()
1152 else if (((wintab + win)->base + (wintab + win)->size - 1) < in decode_win_overlap()
1153 tab->base) in decode_win_overlap()
1159 return (-1); in decode_win_overlap()
1170 win = soc_decode_win_spec->mv_win_cpu_max - 1; in decode_win_cpu_set()
1171 i = -1; in decode_win_cpu_set()
1177 while ((win >= 0) && (win < soc_decode_win_spec->mv_win_cpu_max)) { in decode_win_cpu_set()
1188 if ((win < 0) || (win >= soc_decode_win_spec->mv_win_cpu_max) || in decode_win_cpu_set()
1190 return (-1); in decode_win_cpu_set()
1202 * (capable of remapping) - set remap field with the in decode_win_cpu_set()
1210 cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | in decode_win_cpu_set()
1223 for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) { in decode_win_cpu_setup()
1256 /* Try to match entries from device tree with settings from u-boot */ in decode_win_sdram_fixup()
1274 printf("Disabling SDRAM decoding window: %d\n", j); in decode_win_sdram_fixup()
1375 * DDR SDRAM controller is always 0x0. in ddr_target()
1422 * Armada 38x SoC's equipped with 4GB DRAM in decode_win_cesa_setup()
1433 cr = (((size - 1) & 0xffff0000) | in decode_win_cesa_setup()
1480 if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) in decode_win_usb_dump()
1515 cr = (((ddr_size(i) - 1) & 0xffff0000) | in decode_win_usb_setup()
1570 cr = (((ddr_size(i) - 1) & in decode_win_usb3_setup()
1597 /* ETH encode windows 0-3 have remap capability */ in win_eth_can_remap()
1642 if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) in decode_win_eth_dump()
1688 sz = ((ddr_size(i) - 1) & 0xffff0000); in decode_win_eth_setup()
1773 /* On End-Point only set BAR size to 1MB regardless of DDR size */ in decode_win_pcie_setup()
1783 cr = (ddr_size(i) - 1) & 0xffff0000; in decode_win_pcie_setup()
1807 size -= 0x10000; in decode_win_pcie_setup()
1878 /* IDMA decode windows 0-3 have remap capability */ in win_idma_can_remap()
1912 sz = ((ddr_size(i) - 1) & 0xffff0000); in decode_win_idma_setup()
1914 /* Place DDR entries in non-remapped windows */ in decode_win_idma_setup()
1932 * Remaining targets -- from statically defined table in decode_win_idma_setup()
1938 sz = ((idma_wins[i].size - 1) & 0xffff0000); in decode_win_idma_setup()
1978 if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { in decode_win_idma_valid()
1980 idma_wins_no, MV_WIN_IDMA_MAX - c); in decode_win_idma_valid()
1987 if (wintab->target == 0) { in decode_win_idma_valid()
1993 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { in decode_win_idma_valid()
1995 "val 0x%08x defined\n", i, wintab->remap); in decode_win_idma_valid()
1999 s = wintab->size; in decode_win_idma_valid()
2000 b = wintab->base; in decode_win_idma_valid()
2001 e = b + s - 1; in decode_win_idma_valid()
2002 if (s > (0xFFFFFFFF - b + 1)) { in decode_win_idma_valid()
2013 printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " in decode_win_idma_valid()
2014 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, in decode_win_idma_valid()
2016 idma_wins[j].base + idma_wins[j].size - 1); in decode_win_idma_valid()
2122 /* XOR decode windows 0-3 have remap capability */ in win_xor_can_remap()
2166 sz = ((ddr_size(i) - 1) & 0xffff0000); in xor_active_dram()
2168 /* Place DDR entries in non-remapped windows */ in xor_active_dram()
2202 for (j = 0; j < m; j++, e--) { in decode_win_xor_setup()
2203 /* Number of non-remaped windows */ in decode_win_xor_setup()
2204 window = MV_XOR_NON_REMAP - 1; in decode_win_xor_setup()
2220 * Remaining targets -- from a statically defined table in decode_win_xor_setup()
2227 sz = ((xor_wins[i].size - 1) & 0xffff0000); in decode_win_xor_setup()
2270 if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { in decode_win_xor_valid()
2272 xor_wins_no, MV_WIN_IDMA_MAX - c); in decode_win_xor_valid()
2279 if (wintab->target == 0) { in decode_win_xor_valid()
2285 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { in decode_win_xor_valid()
2287 "val 0x%08x defined\n", i, wintab->remap); in decode_win_xor_valid()
2291 s = wintab->size; in decode_win_xor_valid()
2292 b = wintab->base; in decode_win_xor_valid()
2293 e = b + s - 1; in decode_win_xor_valid()
2294 if (s > (0xFFFFFFFF - b + 1)) { in decode_win_xor_valid()
2307 printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " in decode_win_xor_valid()
2308 "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, in decode_win_xor_valid()
2310 xor_wins[j].base + xor_wins[j].size - 1); in decode_win_xor_valid()
2327 for (j = 0; j < xor_max_eng(); j++, e--) { in decode_win_xor_dump()
2382 cr = ((ddr_size(i) - 1) & 0xffff0000) | in decode_win_sata_setup()
2419 sz = (ddr_size(i) - 1) & in decode_win_ahci_setup()
2431 /* SIZE is set to 16MB - max value */ in decode_win_ahci_setup()
2476 cr = (((ddr_size(i) - 1) & in decode_win_sdhci_setup()
2524 if (node == -1) in fdt_get_ranges()
2599 if ((node = OF_finddevice("sram")) != -1) in win_cpu_from_dt()
2600 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) in win_cpu_from_dt()
2603 if ((node = OF_finddevice("/")) == -1) in win_cpu_from_dt()
2606 if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) in win_cpu_from_dt()
2620 cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target; in win_cpu_from_dt()
2622 cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(0); in win_cpu_from_dt()
2624 cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1); in win_cpu_from_dt()
2633 if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { in win_cpu_from_dt()
2650 cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target; in win_cpu_from_dt()
2651 cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1); in win_cpu_from_dt()
2702 base = fdt_data_get(®[addr_cells - 2], 2); in fdt_win_process_child()
2705 if (soc_node->valid_handler != NULL) in fdt_win_process_child()
2706 if (!soc_node->valid_handler()) in fdt_win_process_child()
2710 if (soc_node->decode_handler != NULL) in fdt_win_process_child()
2711 soc_node->decode_handler(base); in fdt_win_process_child()
2715 if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) in fdt_win_process_child()
2716 soc_node->dump_handler(base); in fdt_win_process_child()
2730 if (node == -1) in fdt_win_setup()
2738 * Traverse through all children of root and simple-bus nodes. in fdt_win_setup()
2748 /* Process Marvell Armada-XP/38x PCIe controllers */ in fdt_win_setup()
2749 if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { in fdt_win_setup()
2754 "assigned-addresses"); in fdt_win_setup()
2763 * Once done with root-level children let's move down to in fdt_win_setup()
2764 * simple-bus and its children. in fdt_win_setup()
2768 sb = node = fdt_find_compatible(node, "simple-bus", 0); in fdt_win_setup()
2774 * Next, move one more level down to internal-regs node (if in fdt_win_setup()
2776 * "simple-bus" compatible. in fdt_win_setup()
2779 node = fdt_find_compatible(node, "simple-bus", 0); in fdt_win_setup()
2800 if ((sb = OF_finddevice("cpu")) != -1) in fdt_fixup_busfreq()
2802 OF_setprop(sb, "bus-frequency", (void *)&freq, in fdt_fixup_busfreq()
2806 * This fixup sets the simple-bus bus-frequency property. in fdt_fixup_busfreq()
2808 if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) in fdt_fixup_busfreq()
2809 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); in fdt_fixup_busfreq()
2821 /* Fix-up SoC ranges according to real fdt_immr_pa */ in fdt_fixup_ranges()
2822 if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { in fdt_fixup_ranges()
2844 /* Fix-up PCIe reg according to real PCIe registers' PA */ in fdt_fixup_ranges()
2865 /* Fix-up succeeded. May return and continue */ in fdt_fixup_ranges()
2882 { "mrvl,DB-88F6281", &fdt_fixup_busfreq },
2883 { "mrvl,DB-78460", &fdt_fixup_busfreq },
2884 { "mrvl,DB-78460", &fdt_fixup_ranges },
2892 if (soc_decode_win_spec->get_tclk != NULL) in get_tclk()
2893 return soc_decode_win_spec->get_tclk(); in get_tclk()
2895 return -1; in get_tclk()
2902 if (soc_decode_win_spec->get_cpu_freq != NULL) in get_cpu_freq()
2903 return soc_decode_win_spec->get_cpu_freq(); in get_cpu_freq()
2905 return -1; in get_cpu_freq()