Lines Matching +full:0 +full:x7f0
47 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \
48 (0x07 & (sar >> 21)))
49 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \
50 (0x0F & (sar >> 24)))
56 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000)
57 #define ARMADAXP_L2_CTRL 0x100
58 #define L2_ENABLE (1 << 0)
59 #define ARMADAXP_L2_AUX_CTRL 0x104
60 #define L2_WBWT_MODE_MASK (3 << 0)
61 #define L2_WBWT_MODE_PAGE 0
68 #define ARMADAXP_L2_CNTR_CTRL 0x200
69 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc)
70 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc)
71 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc)
73 #define ARMADAXP_L2_INT_CAUSE 0x220
75 #define ARMADAXP_L2_SYNC_BARRIER 0x700
76 #define ARMADAXP_L2_INV_WAY 0x778
77 #define ARMADAXP_L2_CLEAN_WAY 0x7BC
78 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0
79 #define ARMADAXP_L2_FLUSH_WAY 0x7FC
81 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200)
82 #define COHER_FABRIC_CTRL 0x00
83 #define COHER_FABRIC_CONF 0x04
84 #define COHER_FABRIC_CFU 0x28
85 #define COHER_FABRIC_CIB_CTRL 0x80
112 return (0); in get_cpu_freq_armadaxp()
135 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1); in platform_get_ncpus()
156 #define ALL_WAYS 0xffffffff
196 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); in armadaxp_l2_init()
206 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); in armadaxp_l2_init()
207 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); in armadaxp_l2_init()
208 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); in armadaxp_l2_init()