Lines Matching +full:0 +full:x00f00000
44 #define VFPSID_IMPLEMENTOR_MASK (0xff000000)
45 #define VFPSID_HARDSOFT_IMP (0x00800000)
48 #define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
49 #define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
50 #define VFP_ARCH1 0x0
51 #define VFP_ARCH2 0x1
52 #define VFP_ARCH3 0x2
54 #define VFPSID_PARTNUMBER_MASK (0x0000ff00)
56 #define VFPSID_VARIANT_MASK (0x000000f0)
57 #define VFPSID_REVISION_MASK 0x0f
60 #define VFPSCR_CC_N (0x80000000) /* comparison less than */
61 #define VFPSCR_CC_Z (0x40000000) /* comparison equal */
62 #define VFPSCR_CC_C (0x20000000) /* comparison = > unordered */
63 #define VFPSCR_CC_V (0x10000000) /* comparison unordered */
64 #define VFPSCR_QC (0x08000000) /* saturation cululative */
65 #define VFPSCR_DN (0x02000000) /* default NaN enable */
66 #define VFPSCR_FZ (0x01000000) /* flush to zero enabled */
69 #define VFPSCR_RMODE_MASK (0x00c00000) /* rounding mode mask */
70 #define VFPSCR_RMODE_RN (0x00000000) /* round nearest */
71 #define VFPSCR_RMODE_RPI (0x00400000) /* round to plus infinity */
72 #define VFPSCR_RMODE_RNI (0x00800000) /* round to neg infinity */
73 #define VFPSCR_RMODE_RM (0x00c00000) /* round to zero */
76 #define VFPSCR_STRIDE_MASK (0x00300000)
78 #define VFPSCR_LEN_MASK (0x00070000)
79 #define VFPSCR_IDE (0x00008000) /* input subnormal exc enable */
80 #define VFPSCR_IXE (0x00001000) /* inexact exception enable */
81 #define VFPSCR_UFE (0x00000800) /* underflow exception enable */
82 #define VFPSCR_OFE (0x00000400) /* overflow exception enable */
83 #define VFPSCR_DNZ (0x00000200) /* div by zero exception en */
84 #define VFPSCR_IOE (0x00000100) /* invalid op exec enable */
85 #define VFPSCR_IDC (0x00000080) /* input subnormal cumul */
86 #define VFPSCR_IXC (0x00000010) /* Inexact cumulative flag */
87 #define VFPSCR_UFC (0x00000008) /* underflow cumulative flag */
88 #define VFPSCR_OFC (0x00000004) /* overflow cumulative flag */
89 #define VFPSCR_DZC (0x00000002) /* division by zero flag */
90 #define VFPSCR_IOC (0x00000001) /* invalid operation cumul */
93 #define VFPEXC_EX (0x80000000) /* exception v1 v2 */
94 #define VFPEXC_EN (0x40000000) /* vfp enable */
95 #define VFPEXC_DEX (0x20000000) /* Synchronous exception */
96 #define VFPEXC_FP2V (0x10000000) /* FPINST2 valid */
97 #define VFPEXC_INV (0x00000080) /* Input exception */
98 #define VFPEXC_UFC (0x00000008) /* Underflow exception */
99 #define VFPEXC_OFC (0x00000004) /* Overflow exception */
100 #define VFPEXC_IOC (0x00000001) /* Invlaid operation */
105 #define VMVFR0_RM_MASK (0xf0000000) /* VFP rounding modes */
108 #define VMVFR0_SV_MASK (0x0f000000) /* VFP short vector supp */
110 #define VMVFR0_SR (0x00f00000) /* VFP hw sqrt supp */
112 #define VMVFR0_D_MASK (0x000f0000) /* VFP divide supp */
114 #define VMVFR0_TE_MASK (0x0000f000) /* VFP trap exception supp */
116 #define VMVFR0_DP_MASK (0x00000f00) /* VFP double prec support */
118 #define VMVFR0_SP_MASK (0x000000f0) /* VFP single prec support */
119 #define VMVFR0_RB_MASK (0x0000000f) /* VFP 64 bit media support */
123 #define VMVFR1_FMAC_MASK (0xf0000000) /* Neon FMAC support */
125 #define VMVFR1_VFP_HP_MASK (0x0f000000) /* VFP half prec support */
127 #define VMVFR1_HP_MASK (0x00f00000) /* Neon half prec support */
129 #define VMVFR1_SP_MASK (0x000f0000) /* Neon single prec support */
131 #define VMVFR1_I_MASK (0x0000f000) /* Neon integer support */
133 #define VMVFR1_LS_MASK (0x00000f00) /* Neon ld/st instr support */
135 #define VMVFR1_DN_MASK (0x000000f0) /* Neon prop NaN support */
136 #define VMVFR1_FZ_MASK (0x0000000f) /* Neon denormal arith supp */
138 #define COPROC10 (0x3 << 20)
139 #define COPROC11 (0x3 << 22)
141 #define FPU_KERN_NORMAL 0x0000
142 #define FPU_KERN_NOWAIT 0x0001
143 #define FPU_KERN_KTHR 0x0002
144 #define FPU_KERN_NOCTX 0x0004