Lines Matching +full:armv6 +full:- +full:capable
1 /*-
53 #define NMRR_WT 2 /* Write Through, Non-Write Allocate */
54 #define NMRR_WB 3 /* Write Back, Non-Write Allocate */
58 * The ARM MMU is capable of mapping memory in the following chunks:
84 /* ARMv6 super-sections. */
86 #define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
91 #define L1_S_OFFSET (L1_S_SIZE - 1)
96 #define L2_L_OFFSET (L2_L_SIZE - 1)
101 #define L2_S_OFFSET (L2_S_SIZE - 1)
130 #define L1_S_SUPERSEC 0x00040000 /* Section is a super-section. */
143 #define L2_TYPE_L 0x01 /* Large Page - 64k - not used yet*/
144 #define L2_TYPE_S 0x02 /* Small Page - 4 */
202 * - L1_AP0 is used as page accessed bit
203 * - L1_AP2 (RO / not RW) is used as page not modified bit
204 * - L1_TEX0 is used as software emulated RO bit
207 #define PTE1_A L1_S_AP0 /* Accessed - software emulated */
208 #define PTE1_NM L1_S_AP2 /* not modified bit - software emulated
217 #define PTE1_RW 0 /* Read-Write (dummy) */
249 * - L2_AP0 is used as page accessed bit
250 * - L2_AP2 (RO / not RW) is used as page not modified bit
251 * - L2_TEX0 is used as software emulated RO bit
254 #define PTE2_A L2_AP0 /* Accessed - software emulated */
255 #define PTE2_NM L2_AP2 /* not modified bit - software emulated
277 (((attr) & L2_TEX0) >> (L2_TEX_SHIFT - L2_CB_SHIFT)))