Lines Matching +full:v7 +full:- +full:r
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Copyright (c) 1994-1996 Mark Brinicombe.
69 /* The high-order byte is always the implementor */
88 /* On recent ARMs this byte holds the architecture and variant (sub-model) */
145 /* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */
165 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
169 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID.
174 #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
177 #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
178 #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
180 #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
223 * Post-ARM3 CP15 registers:
237 * 7 Cache/write-buffer Control
263 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
264 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
266 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
268 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
317 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
318 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
319 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
343 /* Cache type register definitions for ARM v7 */
347 #define CPU_CT_CTYPE_WT 0 /* write-through */
348 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
359 /* ARM v7 Cache type definitions */
370 #define CPUV7_L2CTLR_NPROC(r) ((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1)
407 ((((fsr) & (1 << 10)) >> (10 - 4))))
409 #define FSR_WNR (1 << 11) /* Write-not-Read access */
429 * +-------+-------------------------------------------------------+
432 * +-------+-------------------------------------------------------+