Lines Matching +full:mini +full:- +full:core
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
7 * Copyright (c) 1994-1996 Mark Brinicombe.
69 /* The high-order byte is always the implementor */
88 /* On recent ARMs this byte holds the architecture and variant (sub-model) */
104 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
105 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
145 /* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */
163 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
164 #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */
165 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
168 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported
169 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID.
174 #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
177 #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
178 #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
180 #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
185 #define CPU_ID_PXA250 0x69052100 /* sans core revision */
187 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
188 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
189 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
190 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
191 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
192 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
223 * Post-ARM3 CP15 registers:
237 * 7 Cache/write-buffer Control
263 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
264 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
266 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
316 /* Note: XSCale core 3 uses those for LLR DCcahce attributes */
317 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
318 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
319 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
322 /* Xscale Core 3 only */
347 #define CPU_CT_CTYPE_WT 0 /* write-through */
348 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
407 ((((fsr) & (1 << 10)) >> (10 - 4))))
409 #define FSR_WNR (1 << 11) /* Write-not-Read access */
429 * +-------+-------------------------------------------------------+
432 * +-------+-------------------------------------------------------+