Lines Matching +full:0 +full:x51000000
44 #define PSR_MODE 0x0000001f /* mode mask */
45 #define PSR_USR32_MODE 0x00000010
46 #define PSR_FIQ32_MODE 0x00000011
47 #define PSR_IRQ32_MODE 0x00000012
48 #define PSR_SVC32_MODE 0x00000013
49 #define PSR_MON32_MODE 0x00000016
50 #define PSR_ABT32_MODE 0x00000017
51 #define PSR_HYP32_MODE 0x0000001a
52 #define PSR_UND32_MODE 0x0000001b
53 #define PSR_SYS32_MODE 0x0000001f
54 #define PSR_32_MODE 0x00000010
55 #define PSR_T 0x00000020 /* Instruction set bit */
56 #define PSR_F 0x00000040 /* FIQ disable bit */
57 #define PSR_I 0x00000080 /* IRQ disable bit */
58 #define PSR_A 0x00000100 /* Imprecise abort bit */
59 #define PSR_E 0x00000200 /* Data endianess bit */
60 #define PSR_GE 0x000f0000 /* Greater than or equal to bits */
61 #define PSR_J 0x01000000 /* Java bit */
62 #define PSR_Q 0x08000000 /* Sticky overflow bit */
63 #define PSR_V 0x10000000 /* Overflow bit */
64 #define PSR_C 0x20000000 /* Carry bit */
65 #define PSR_Z 0x40000000 /* Zero bit */
66 #define PSR_N 0x80000000 /* Negative bit */
67 #define PSR_FLAGS 0xf0000000 /* Flags mask. */
70 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
71 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */
72 #define CPU_ID_DEC 0x44000000 /* 'D' */
73 #define CPU_ID_MOTOROLA 0x4D000000 /* 'M' */
74 #define CPU_ID_QUALCOM 0x51000000 /* 'Q' */
75 #define CPU_ID_TI 0x54000000 /* 'T' */
76 #define CPU_ID_MARVELL 0x56000000 /* 'V' */
77 #define CPU_ID_INTEL 0x69000000 /* 'i' */
78 #define CPU_ID_FARADAY 0x66000000 /* 'f' */
81 #define CPU_ID_VARIANT_MASK 0x00f00000
84 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000)
85 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000)
89 #define CPU_ID_ARCH_MASK 0x000f0000
90 #define CPU_ID_ARCH_V3 0x00000000
91 #define CPU_ID_ARCH_V4 0x00010000
92 #define CPU_ID_ARCH_V4T 0x00020000
93 #define CPU_ID_ARCH_V5 0x00030000
94 #define CPU_ID_ARCH_V5T 0x00040000
95 #define CPU_ID_ARCH_V5TE 0x00050000
96 #define CPU_ID_ARCH_V5TEJ 0x00060000
97 #define CPU_ID_ARCH_V6 0x00070000
98 #define CPU_ID_CPUID_SCHEME 0x000f0000
101 #define CPU_ID_PARTNO_MASK 0x0000fff0
104 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */
105 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */
106 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */
109 #define CPU_ID_REVISION_MASK 0x0000000f
112 #define CPU_ID_CPU_MASK 0xfffffff0
115 #define CPU_ID_ARM920T 0x41129200
116 #define CPU_ID_ARM920T_ALT 0x41009200
117 #define CPU_ID_ARM922T 0x41029220
118 #define CPU_ID_ARM926EJS 0x41069260
119 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */
120 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */
121 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */
122 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */
123 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */
124 #define CPU_ID_ARM1022ES 0x4105a220
125 #define CPU_ID_ARM1026EJS 0x4106a260
126 #define CPU_ID_ARM1136JS 0x4107b360
127 #define CPU_ID_ARM1136JSR1 0x4117b360
128 #define CPU_ID_ARM1176JZS 0x410fb760
134 #define CPU_ID_CORTEXA5 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc050)
135 #define CPU_ID_CORTEXA7 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc070)
136 #define CPU_ID_CORTEXA8 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc080)
140 #define CPU_ID_CORTEXA9 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc090)
146 #define CPU_ID_CORTEXA12 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0)
147 #define CPU_ID_CORTEXA12R0 (CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT))
148 #define CPU_ID_CORTEXA15 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0)
149 #define CPU_ID_CORTEXA15R0 (CPU_ID_CORTEXA15 | (0 << CPU_ID_VARIANT_SHIFT))
153 #define CPU_ID_CORTEXA53 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd030)
154 #define CPU_ID_CORTEXA57 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd070)
155 #define CPU_ID_CORTEXA72 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd080)
157 #define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME | 0x06f0)
159 #define CPU_ID_KRAIT300R0 (CPU_ID_KRAIT300 | (0 << CPU_ID_VARIANT_SHIFT))
162 #define CPU_ID_TI925T 0x54029250
163 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */
164 #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */
165 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */
168 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported
169 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID.
172 #define CPU_ID_MV88FR571_41 0x00000000
174 #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
177 #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
178 #define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
180 #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
182 #define CPU_ID_FA526 0x66015260
183 #define CPU_ID_FA626TE 0x66056260
184 #define CPU_ID_80200 0x69052000
185 #define CPU_ID_PXA250 0x69052100 /* sans core revision */
186 #define CPU_ID_PXA210 0x69052120
187 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */
188 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */
189 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */
190 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */
191 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */
192 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */
193 #define CPU_ID_PXA27X 0x69054110
194 #define CPU_ID_80321_400 0x69052420
195 #define CPU_ID_80321_600 0x69052430
196 #define CPU_ID_80321_400_B0 0x69052c20
197 #define CPU_ID_80321_600_B0 0x69052c30
198 #define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */
199 #define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */
200 #define CPU_ID_81342 0x69056810
201 #define CPU_ID_IXP425 0x690541c0
202 #define CPU_ID_IXP425_533 0x690541c0
203 #define CPU_ID_IXP425_400 0x690541d0
204 #define CPU_ID_IXP425_266 0x690541f0
205 #define CPU_ID_IXP435 0x69054040
206 #define CPU_ID_IXP465 0x69054200
209 #define ARM_PFR0_ARM_ISA_MASK 0x0000000f
211 #define ARM_PFR0_THUMB_MASK 0x000000f0
212 #define ARM_PFR0_THUMB 0x10
213 #define ARM_PFR0_THUMB2 0x30
215 #define ARM_PFR0_JAZELLE_MASK 0x00000f00
216 #define ARM_PFR0_THUMBEE_MASK 0x0000f000
218 #define ARM_PFR1_ARMV4_MASK 0x0000000f
219 #define ARM_PFR1_SEC_EXT_MASK 0x000000f0
220 #define ARM_PFR1_MICROCTRL_MASK 0x00000f00
259 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */
260 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
261 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */
262 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
263 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
264 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
265 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
266 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
267 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
268 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
269 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
270 #define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */
271 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
272 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
273 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
274 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
275 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
276 #define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */
277 #define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
278 #define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
279 #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
280 #define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
281 #define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
282 #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
283 #define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
284 #define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/
285 #define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */
286 #define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
291 #define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
292 #define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
293 #define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */
294 #define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */
295 #define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
296 #define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */
297 #define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
298 #define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
301 #define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
308 #define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
309 #define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
310 #define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
311 #define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
314 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
315 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
317 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */
318 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
319 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */
320 #define XSCALE_AUXCTL_MD_MASK 0x00000030
323 #define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */
325 /* Marvell Extra Features Register (CP15 register 1, opcode2 0) */
326 #define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */
327 #define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */
328 #define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */
329 #define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */
330 #define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
331 #define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */
332 #define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */
333 #define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */
334 #define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */
335 #define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */
338 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */
339 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */
341 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
344 #define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */
345 #define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */
347 #define CPU_CT_CTYPE_WT 0 /* write-through */
353 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */
355 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */
356 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */
358 #define CPU_CT_ARMV7 0x4
365 #define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */
366 #define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */
367 #define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */
372 #define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7)
373 #define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7)
374 #define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7)
375 #define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7)
383 #define FAULT_USER 0x10
385 #define FAULT_ALIGN 0x001 /* Alignment Fault */
386 #define FAULT_DEBUG 0x002 /* Debug Event */
387 #define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */
388 #define FAULT_ICACHE 0x004 /* Instruction cache maintenance */
389 #define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */
390 #define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */
391 #define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */
392 #define FAULT_EA_PREC 0x008 /* External Abort */
393 #define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */
394 #define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */
395 #define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */
396 #define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */
397 #define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */
398 #define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */
399 #define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */
400 #define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */
401 #define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */
402 #define FAULT_PARITY 0x019 /* Parity Error */
403 #define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */
404 #define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */
406 #define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \
417 #define ARM_VECTORS_LOW 0x00000000U
418 #define ARM_VECTORS_HIGH 0xffff0000U
420 #define ARM_VECTORS_LOW 0
421 #define ARM_VECTORS_HIGH 0xffff0000
428 * 1 0 9 8 7 0
436 #define INSN_COND_MASK 0xf0000000 /* Condition mask */
437 #define INSN_COND_AL 0xe0000000 /* Always condition */
448 #define ARM_CP15_HDCR_HPMN 0x0000001f