Lines Matching +full:enable +full:- +full:modem +full:- +full:interrupt
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
64 #define UART_MODEM 0x0D /* Modem Register */
74 #define UART_IE7816 0x19 /* 7816 Interrupt Enable Register */
75 #define UART_IS7816 0x1A /* 7816 Interrupt Status Register */
82 #define UART_C6 0x21 /* CEA709.1-B Control Register 6 */
83 #define UART_PCTH 0x22 /* CEA709.1-B Packet Cycle Time Counter High */
84 #define UART_PCTL 0x23 /* CEA709.1-B Packet Cycle Time Counter Low */
85 #define UART_B1T 0x24 /* CEA709.1-B Beta1 Timer */
86 #define UART_SDTH 0x25 /* CEA709.1-B Secondary Delay Timer High */
87 #define UART_SDTL 0x26 /* CEA709.1-B Secondary Delay Timer Low */
88 #define UART_PRE 0x27 /* CEA709.1-B Preamble */
89 #define UART_TPL 0x28 /* CEA709.1-B Transmit Packet Length */
90 #define UART_IE 0x29 /* CEA709.1-B Interrupt Enable Register */
91 #define UART_WB 0x2A /* CEA709.1-B WBASE */
92 #define UART_S3 0x2B /* CEA709.1-B Status Register */
93 #define UART_S4 0x2C /* CEA709.1-B Status Register */
94 #define UART_RPL 0x2D /* CEA709.1-B Received Packet Length */
95 #define UART_RPREL 0x2E /* CEA709.1-B Received Preamble Length */
96 #define UART_CPW 0x2F /* CEA709.1-B Collision Pulse Width */
97 #define UART_RIDT 0x30 /* CEA709.1-B Receive Indeterminate Time */
98 #define UART_TIDT 0x31 /* CEA709.1-B Transmit Indeterminate Time */
100 #define UART_C2_TE (1 << 3) /* Transmitter Enable */
101 #define UART_C2_TIE (1 << 7) /* Transmitter Interrupt Enable */
102 #define UART_C2_RE (1 << 2) /* Receiver Enable */
103 #define UART_C2_RIE (1 << 5) /* Receiver Interrupt Enable */
106 #define UART_S2_LBKDIF (1 << 7) /* LIN Break Detect Interrupt Flag */
112 * Low-level UART interface.
192 * High-level UART interface.
206 bas = &sc->sc_bas; in uart_reinit()
225 brfa = (clkspeed / baud) - (sbr * 16); in uart_reinit()
284 {"fsl,mvf600-uart", (uintptr_t)&uart_vybrid_class},
295 bas = &sc->sc_bas; in vf_uart_bus_attach()
297 sc->sc_hwiflow = 0; in vf_uart_bus_attach()
298 sc->sc_hwoflow = 0; in vf_uart_bus_attach()
303 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { in vf_uart_bus_attach()
343 uart_lock(sc->sc_hwmtx); in vf_uart_bus_ioctl()
356 uart_unlock(sc->sc_hwmtx); in vf_uart_bus_ioctl()
369 bas = &sc->sc_bas; in vf_uart_bus_ipend()
372 uart_lock(sc->sc_hwmtx); in vf_uart_bus_ipend()
386 if (sc->sc_txbusy != 0) { in vf_uart_bus_ipend()
403 uart_unlock(sc->sc_hwmtx); in vf_uart_bus_ipend()
413 uart_lock(sc->sc_hwmtx); in vf_uart_bus_param()
414 vf_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); in vf_uart_bus_param()
415 uart_unlock(sc->sc_hwmtx); in vf_uart_bus_param()
425 error = vf_uart_probe(&sc->sc_bas); in vf_uart_bus_probe()
429 sc->sc_rxfifosz = 1; in vf_uart_bus_probe()
430 sc->sc_txfifosz = 1; in vf_uart_bus_probe()
432 device_set_desc(sc->sc_dev, "Vybrid Family UART"); in vf_uart_bus_probe()
443 bas = &sc->sc_bas; in vf_uart_bus_receive()
444 uart_lock(sc->sc_hwmtx); in vf_uart_bus_receive()
450 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; in vf_uart_bus_receive()
458 /* Reenable Data Ready interrupt */ in vf_uart_bus_receive()
463 uart_unlock(sc->sc_hwmtx); in vf_uart_bus_receive()
476 /* Enable RX interrupt */ in vf_uart_bus_setsig()
477 bas = &sc->sc_bas; in vf_uart_bus_setsig()
478 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { in vf_uart_bus_setsig()
490 struct uart_bas *bas = &sc->sc_bas; in vf_uart_bus_transmit()
494 bas = &sc->sc_bas; in vf_uart_bus_transmit()
495 uart_lock(sc->sc_hwmtx); in vf_uart_bus_transmit()
498 for (i = 0; i < sc->sc_txdatasz; i++) { in vf_uart_bus_transmit()
499 uart_setreg(bas, UART_D, sc->sc_txbuf[i] & 0xff); in vf_uart_bus_transmit()
500 uart_barrier(&sc->sc_bas); in vf_uart_bus_transmit()
503 sc->sc_txbusy = 1; in vf_uart_bus_transmit()
510 uart_unlock(sc->sc_hwmtx); in vf_uart_bus_transmit()