Lines Matching +full:0 +full:x11d
29 #define DMA_CR 0x000 /* Control */
30 #define DMA_ES 0x004 /* Error Status */
31 #define DMA_ERQ 0x00C /* Enable Request */
32 #define DMA_EEI 0x014 /* Enable Error Interrupt */
33 #define DMA_CEEI 0x018 /* Clear Enable Error Interrupt */
34 #define DMA_SEEI 0x019 /* Set Enable Error Interrupt */
35 #define DMA_CERQ 0x01A /* Clear Enable Request */
36 #define DMA_SERQ 0x01B /* Set Enable Request */
37 #define DMA_CDNE 0x01C /* Clear DONE Status Bit */
38 #define DMA_SSRT 0x01D /* Set START Bit */
39 #define DMA_CERR 0x01E /* Clear Error */
41 #define DMA_CINT 0x01F /* Clear Interrupt Request */
43 #define DMA_INT 0x024 /* Interrupt Request */
44 #define DMA_ERR 0x02C /* Error */
45 #define DMA_HRS 0x034 /* Hardware Request Status */
46 #define DMA_EARS 0x044 /* Enable Asynchronous Request in Stop */
47 #define DMA_DCHPRI3 0x100 /* Channel n Priority */
48 #define DMA_DCHPRI2 0x101 /* Channel n Priority */
49 #define DMA_DCHPRI1 0x102 /* Channel n Priority */
50 #define DMA_DCHPRI0 0x103 /* Channel n Priority */
51 #define DMA_DCHPRI7 0x104 /* Channel n Priority */
52 #define DMA_DCHPRI6 0x105 /* Channel n Priority */
53 #define DMA_DCHPRI5 0x106 /* Channel n Priority */
54 #define DMA_DCHPRI4 0x107 /* Channel n Priority */
55 #define DMA_DCHPRI11 0x108 /* Channel n Priority */
56 #define DMA_DCHPRI10 0x109 /* Channel n Priority */
57 #define DMA_DCHPRI9 0x10A /* Channel n Priority */
58 #define DMA_DCHPRI8 0x10B /* Channel n Priority */
59 #define DMA_DCHPRI15 0x10C /* Channel n Priority */
60 #define DMA_DCHPRI14 0x10D /* Channel n Priority */
61 #define DMA_DCHPRI13 0x10E /* Channel n Priority */
62 #define DMA_DCHPRI12 0x10F /* Channel n Priority */
63 #define DMA_DCHPRI19 0x110 /* Channel n Priority */
64 #define DMA_DCHPRI18 0x111 /* Channel n Priority */
65 #define DMA_DCHPRI17 0x112 /* Channel n Priority */
66 #define DMA_DCHPRI16 0x113 /* Channel n Priority */
67 #define DMA_DCHPRI23 0x114 /* Channel n Priority */
68 #define DMA_DCHPRI22 0x115 /* Channel n Priority */
69 #define DMA_DCHPRI21 0x116 /* Channel n Priority */
70 #define DMA_DCHPRI20 0x117 /* Channel n Priority */
71 #define DMA_DCHPRI27 0x118 /* Channel n Priority */
72 #define DMA_DCHPRI26 0x119 /* Channel n Priority */
73 #define DMA_DCHPRI25 0x11A /* Channel n Priority */
74 #define DMA_DCHPRI24 0x11B /* Channel n Priority */
75 #define DMA_DCHPRI31 0x11C /* Channel n Priority */
76 #define DMA_DCHPRI30 0x11D /* Channel n Priority */
77 #define DMA_DCHPRI29 0x11E /* Channel n Priority */
78 #define DMA_DCHPRI28 0x11F /* Channel n Priority */
80 #define DMA_TCDn_SADDR(n) (0x00 + 0x20 * n) /* Source Address */
81 #define DMA_TCDn_SOFF(n) (0x04 + 0x20 * n) /* Signed Source Address Offset */
82 #define DMA_TCDn_ATTR(n) (0x06 + 0x20 * n) /* Transfer Attributes */
83 #define DMA_TCDn_NBYTES_MLNO(n) (0x08 + 0x20 * n) /* Minor Byte Count */
84 #define DMA_TCDn_NBYTES_MLOFFNO(n) (0x08 + 0x20 * n) /* Signed Minor Loop Offset */
85 #define DMA_TCDn_NBYTES_MLOFFYES(n) (0x08 + 0x20 * n) /* Signed Minor Loop Offset */
86 #define DMA_TCDn_SLAST(n) (0x0C + 0x20 * n) /* Last Source Address Adjustment */
87 #define DMA_TCDn_DADDR(n) (0x10 + 0x20 * n) /* Destination Address */
88 #define DMA_TCDn_DOFF(n) (0x14 + 0x20 * n) /* Signed Destination Address Offset */
89 #define DMA_TCDn_CITER_ELINKYES(n) (0x16 + 0x20 * n) /* Current Minor Loop Link, Major Loop Count */
90 #define DMA_TCDn_CITER_ELINKNO(n) (0x16 + 0x20 * n)
91 #define DMA_TCDn_DLASTSGA(n) (0x18 + 0x20 * n) /* Last Dst Addr Adjustment/Scatter Gather Address …
92 #define DMA_TCDn_CSR(n) (0x1C + 0x20 * n) /* Control and Status */
93 #define DMA_TCDn_BITER_ELINKYES(n) (0x1E + 0x20 * n) /* Beginning Minor Loop Link, Major Loop Count…
94 #define DMA_TCDn_BITER_ELINKNO(n) (0x1E + 0x20 * n) /* Beginning Minor Loop Link, Major Loop Count …
96 #define TCD_CSR_START (1 << 0)
109 #define TCD_ATTR_DSIZE_SHIFT 0 /* Dst Data Transfer Size */