Lines Matching refs:sel_val
162 uint32_t sel_val; member
174 .sel_val = 0,
198 .sel_val = 0,
210 .sel_val = 0x3, /* Divided PLL4 main clock */
222 .sel_val = CKO1_PLL4_DIVD,
234 .sel_val = 0,
246 .sel_val = 0,
258 .sel_val = 0,
270 .sel_val = 0,
282 .sel_val = 0,
294 .sel_val = 0,
314 .sel_val = 0x3, /* Divided PLL4 main clock */
379 reg |= (clk->sel_val << clk->sel_shift); in set_clock()