1 /*-
8  * 1. Redistributions of source code must retain the above copyright
31  * Rev. 1, 04/2013
60 	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
62 	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
64 #define	SSI_NCHANNELS	1
74 #define	 SCR_I2S_MODE_S	5    /* I2S Mode Select. */
76 #define	 SCR_SYN	(1 << 4)
77 #define	 SCR_NET       	(1 << 3)  /* Network mode */
78 #define	 SCR_RE		(1 << 2)  /* Receive Enable. */
79 #define	 SCR_TE		(1 << 1)  /* Transmit Enable. */
80 #define	 SCR_SSIEN	(1 << 0)  /* SSI Enable */
83 #define	 SIER_RDMAE	(1 << 22) /* Receive DMA Enable. */
84 #define	 SIER_RIE	(1 << 21) /* Receive Interrupt Enable. */
85 #define	 SIER_TDMAE	(1 << 20) /* Transmit DMA Enable. */
86 #define	 SIER_TIE	(1 << 19) /* Transmit Interrupt Enable. */
87 #define	 SIER_TDE0IE	(1 << 12) /* Transmit Data Register Empty 0. */
88 #define	 SIER_TUE0IE	(1 << 8)  /* Transmitter Underrun Error 0. */
89 #define	 SIER_TFE0IE	(1 << 0)  /* Transmit FIFO Empty 0 IE. */
91 #define	 STCR_TXBIT0	(1 << 9)  /* Transmit Bit 0 shift MSB/LSB */
92 #define	 STCR_TFEN1	(1 << 8)  /* Transmit FIFO Enable 1. */
93 #define	 STCR_TFEN0	(1 << 7)  /* Transmit FIFO Enable 0. */
94 #define	 STCR_TFDIR	(1 << 6)  /* Transmit Frame Direction. */
95 #define	 STCR_TXDIR	(1 << 5)  /* Transmit Clock Direction. */
96 #define	 STCR_TSHFD	(1 << 4)  /* Transmit Shift Direction. */
97 #define	 STCR_TSCKP	(1 << 3)  /* Transmit Clock Polarity. */
98 #define	 STCR_TFSI	(1 << 2)  /* Transmit Frame Sync Invert. */
99 #define	 STCR_TFSL	(1 << 1)  /* Transmit Frame Sync Length. */
100 #define	 STCR_TEFS	(1 << 0)  /* Transmit Early Frame Sync. */
103 #define	 STCCR_DIV2	(1 << 18) /* Divide By 2. */
104 #define	 STCCR_PSR	(1 << 17) /* Divide clock by 8. */
113 #define	 SFCSR_RFWM1_S	20	/* Receive FIFO Empty WaterMark 1 */
115 #define	 SFCSR_TFWM1_S	16	/* Transmit FIFO Empty WaterMark 1 */
153  *     (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
156  *  Fref ------/     |     |      |    |   |   |   |   |   |   |
157  *  PLL4 div select -/     |      |    |   |   |   |   |   |   |
158  *  PLL4 num --------------/      |    |   |   |   |   |   |   |
159  *  PLL4 denom -------------------/    |   |   |   |   |   |   |
160  *  PLL4 post div ---------------------/   |   |   |   |   |   |
161  *  CCM ssi pre div (CCM_CS1CDR) ----------/   |   |   |   |   |
162  *  CCM ssi post div (CCM_CS1CDR) -------------/   |   |   |   |
163  *  SSI PM7_PM0_S ---------------------------------/   |   |   |
164  *  SSI Fixed divider ---------------------------------/   |   |
165  *  SSI DIV2 ----------------------------------------------/   |
166  *  SSI PSR (prescaler /1 or /8) ------------------------------/
218 	{ -1, 0 }
237 	sc = scp->sc;  in ssimixer_init()
240 		return -1;  in ssimixer_init()
245 	mtx_lock(&sc->lock);  in ssimixer_init()
246 	pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);  in ssimixer_init()
248 	mtx_unlock(&sc->lock);  in ssimixer_init()
263 #if 1  in ssimixer_set()
264 	device_printf(scp->dev, "ssimixer_set() %d %d\n",  in ssimixer_set()
291 	sc = scp->sc;  in ssichan_init()
293 	mtx_lock(&sc->lock);  in ssichan_init()
294 	ch = &scp->chan[0];  in ssichan_init()
295 	ch->dir = dir;  in ssichan_init()
296 	ch->run = 0;  in ssichan_init()
297 	ch->buffer = b;  in ssichan_init()
298 	ch->channel = c;  in ssichan_init()
299 	ch->parent = scp;  in ssichan_init()
300 	mtx_unlock(&sc->lock);  in ssichan_init()
302 	if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {  in ssichan_init()
303 		device_printf(scp->dev, "Can't setup sndbuf.\n");  in ssichan_init()
314 	struct sc_pcminfo *scp = ch->parent;  in ssichan_free()
315 	struct sc_info *sc = scp->sc;  in ssichan_free()
318 	device_printf(scp->dev, "ssichan_free()\n");  in ssichan_free()
321 	mtx_lock(&sc->lock);  in ssichan_free()
323 	mtx_unlock(&sc->lock);  in ssichan_free()
333 	ch->format = format;  in ssichan_setformat()
349 	scp = ch->parent;  in ssichan_setspeed()
350 	sc = scp->sc;  in ssichan_setspeed()
364 			threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?  in ssichan_setspeed()
365 			    ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);  in ssichan_setspeed()
371 	sc->sr = sr;  in ssichan_setspeed()
375 	return (sr->speed);  in ssichan_setspeed()
383 	sr = sc->sr;  in ssi_configure_clock()
385 	pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);  in ssi_configure_clock()
394 	struct sc_pcminfo *scp = ch->parent;  in ssichan_setblocksize()
395 	struct sc_info *sc = scp->sc;  in ssichan_setblocksize()
397 	sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);  in ssichan_setblocksize()
401 	return (ch->buffer->blksz);  in ssichan_setblocksize()
414 	ch = &scp->chan[0];  in ssi_dma_intr()
415 	sc = scp->sc;  in ssi_dma_intr()
416 	conf = sc->conf;  in ssi_dma_intr()
418 	bufsize = ch->buffer->bufsize;  in ssi_dma_intr()
420 	sc->pos += conf->period;  in ssi_dma_intr()
421 	if (sc->pos >= bufsize)  in ssi_dma_intr()
422 		sc->pos -= bufsize;  in ssi_dma_intr()
424 	if (ch->run)  in ssi_dma_intr()
425 		chn_intr(ch->channel);  in ssi_dma_intr()
439 	if ((node = ofw_bus_get_node(sc->dev)) == -1)  in find_sdma_controller()
446 		device_printf(sc->dev,  in find_sdma_controller()
454 	sc->sdma_ev_rx = dts_value[1];  in find_sdma_controller()
455 	sc->sdma_ev_tx = dts_value[5];  in find_sdma_controller()
464 		device_printf(sc->dev, "No sDMA found. Can't operate\n");  in find_sdma_controller()
468 	sc->sdma_sc = sdma_sc;  in find_sdma_controller()
481 	ch = &scp->chan[0];  in setup_dma()
482 	sc = scp->sc;  in setup_dma()
483 	conf = sc->conf;  in setup_dma()
485 	conf->ih = ssi_dma_intr;  in setup_dma()
486 	conf->ih_user = scp;  in setup_dma()
487 	conf->saddr = sc->buf_base_phys;  in setup_dma()
488 	conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;  in setup_dma()
489 	conf->event = sc->sdma_ev_tx; /* SDMA TX event */  in setup_dma()
490 	conf->period = ch->buffer->blksz;  in setup_dma()
491 	conf->num_bd = ch->buffer->blkcnt;  in setup_dma()
500 	fmt = ch->buffer->fmt;  in setup_dma()
503 		conf->word_length = 16;  in setup_dma()
504 		conf->command = CMD_2BYTES;  in setup_dma()
506 		conf->word_length = 24;  in setup_dma()
507 		conf->command = CMD_3BYTES;  in setup_dma()
509 		device_printf(sc->dev, "Unknown format\n");  in setup_dma()
510 		return (-1);  in setup_dma()
522 	sc = scp->sc;  in ssi_start()
524 	if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {  in ssi_start()
525 		device_printf(sc->dev, "Can't configure sDMA\n");  in ssi_start()
526 		return (-1);  in ssi_start()
533 	sdma_start(sc->sdma_channel);  in ssi_start()
544 	sc = scp->sc;  in ssi_stop()
550 	sdma_stop(sc->sdma_channel);  in ssi_stop()
552 	bzero(sc->buf_base, sc->dma_size);  in ssi_stop()
565 	scp = ch->parent;  in ssichan_trigger()
566 	sc = scp->sc;  in ssichan_trigger()
568 	mtx_lock(&sc->lock);  in ssichan_trigger()
573 		device_printf(scp->dev, "trigger start\n");  in ssichan_trigger()
575 		ch->run = 1;  in ssichan_trigger()
584 		device_printf(scp->dev, "trigger stop or abort\n");  in ssichan_trigger()
586 		ch->run = 0;  in ssichan_trigger()
593 	mtx_unlock(&sc->lock);  in ssichan_trigger()
606 	scp = ch->parent;  in ssichan_getptr()
607 	sc = scp->sc;  in ssichan_getptr()
609 	return (sc->pos);  in ssichan_getptr()
646 	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))  in ssi_probe()
661 	sc = scp->sc;  in ssi_intr()
666 	device_printf(scp->sc->dev, "SSI Intr 0x%08x\n",  in ssi_intr()
680 	reg |= (1 << DC4_DC0_S); /* 2 words per frame */  in setup_ssi()
681 	reg &= ~(STCCR_DIV2); /* Divide by 1 */  in setup_ssi()
682 	reg &= ~(STCCR_PSR); /* Divide by 1 */  in setup_ssi()
684 	reg |= (1 << PM7_PM0_S); /* Divide by 2 */  in setup_ssi()
734 	sc->dev = dev;  in ssi_attach()
735 	sc->sr = &rate_map[0];  in ssi_attach()
736 	sc->pos = 0;  in ssi_attach()
737 	sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);  in ssi_attach()
739 	mtx_init(&sc->lock, device_get_nameunit(dev), "ssi softc", MTX_DEF);  in ssi_attach()
741 	if (bus_alloc_resources(dev, ssi_spec, sc->res)) {  in ssi_attach()
747 	sc->bst = rman_get_bustag(sc->res[0]);  in ssi_attach()
748 	sc->bsh = rman_get_bushandle(sc->res[0]);  in ssi_attach()
758 	scp->sc = sc;  in ssi_attach()
759 	scp->dev = dev;  in ssi_attach()
765 	sc->dma_size = 131072;  in ssi_attach()
773 	    bus_get_dma_tag(sc->dev),  in ssi_attach()
774 	    4, sc->dma_size,		/* alignment, boundary */  in ssi_attach()
778 	    sc->dma_size, 1,		/* maxsize, nsegments */  in ssi_attach()
779 	    sc->dma_size, 0,		/* maxsegsize, flags */  in ssi_attach()
781 	    &sc->dma_tag);  in ssi_attach()
783 	err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,  in ssi_attach()
784 	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);  in ssi_attach()
790 	err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,  in ssi_attach()
791 	    sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);  in ssi_attach()
797 	bzero(sc->buf_base, sc->dma_size);  in ssi_attach()
800 	err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,  in ssi_attach()
801 	    NULL, ssi_intr, scp, &sc->ih);  in ssi_attach()
811 	scp->chnum = 0;  in ssi_attach()
813 	scp->chnum++;  in ssi_attach()
827 	sc->sdma_channel = sdma_alloc();  in ssi_attach()
828 	if (sc->sdma_channel < 0) {  in ssi_attach()
829 		device_printf(sc->dev, "Can't get sDMA channel\n");  in ssi_attach()
830 		return (1);  in ssi_attach()
851 MODULE_VERSION(ssi, 1);