Lines Matching full:transmit
69 #define SSI_STX0 0x00 /* Transmit Data Register n */
70 #define SSI_STX1 0x04 /* Transmit Data Register n */
79 #define SCR_TE (1 << 1) /* Transmit Enable. */
85 #define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */
86 #define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */
87 #define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */
89 #define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */
90 #define SSI_STCR 0x1C /* Transmit Configuration Register */
91 #define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */
92 #define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */
93 #define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */
94 #define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */
95 #define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */
96 #define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */
97 #define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */
98 #define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */
99 #define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */
100 #define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */
102 #define SSI_STCCR 0x24 /* Transmit Clock Control Register */
115 #define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */
119 #define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */
125 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */