375 	const struct videomode 	*sc_mode;  member
658 	freq = sc->sc_mode->dot_clock * 1000;  in ipu_config_timing()
681 	    sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE);  in ipu_config_timing()
687 	    sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK);  in ipu_config_timing()
690 	    0, MODE_HSW(sc->sc_mode) * 2);  in ipu_config_timing()
694 	    sc->sc_mode->vtotal - 1, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC),  in ipu_config_timing()
699 	    0, MODE_VSW(sc->sc_mode) * 2);  in ipu_config_timing()
702 	IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1);  in ipu_config_timing()
709 	    MODE_VSW(sc->sc_mode) + MODE_VFP(sc->sc_mode), DI_SYNC_COUNTER(DI_COUNTER_HSYNC));  in ipu_config_timing()
711 	    sc->sc_mode->vdisplay, DI_SYNC_COUNTER(DI_COUNTER_VSYNC),  in ipu_config_timing()
715 	    0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK);  in ipu_config_timing()
717 	    sc->sc_mode->hdisplay, DI_SYNC_COUNTER(DI_COUNTER_AD_0),  in ipu_config_timing()
730 	if (sc->sc_mode->flags & VID_NHSYNC)  in ipu_config_timing()
735 	if (sc->sc_mode->flags & VID_NVSYNC)  in ipu_config_timing()
757 	IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay);  in ipu_config_timing()
872 	stride = sc->sc_mode->hdisplay * MODE_BPP / 8;  in ipu_init_buffer()
877 	CH_PARAM_SET_FW(&param, sc->sc_mode->hdisplay - 1);  in ipu_init_buffer()
878 	CH_PARAM_SET_FH(&param, sc->sc_mode->vdisplay - 1);  in ipu_init_buffer()
985 	dma_size = round_page(sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * (MODE_BPP / 8));  in ipu_init()
1020 	sc->sc_fb_size = sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * MODE_BPP / 8;  in ipu_init()
1044 	sc->sc_fb_info.fb_stride = sc->sc_mode->hdisplay * MODE_BPP / 8;  in ipu_init()
1045 	sc->sc_fb_info.fb_width = sc->sc_mode->hdisplay;  in ipu_init()
1046 	sc->sc_fb_info.fb_height = sc->sc_mode->vdisplay;  in ipu_init()
1142 	sc->sc_mode = videomode;  in ipu_hdmi_event()
1150 	CRTC_SET_VIDEOMODE(hdmi_dev, sc->sc_mode);  in ipu_hdmi_event()