83 #define	IPU_READ4(_sc, reg)	bus_read_4((_sc)->sc_mem_res, (reg))  macro
512 	reg = IPU_READ4(sc, IPU_DISP_GEN);  in ipu_di_enable()
555 	reg = IPU_READ4(sc, addr);  in ipu_config_wave_gen_1()
583 	reg = IPU_READ4(sc, addr);  in ipu_reset_wave_gen()
728 	gen = IPU_READ4(sc, gen_offset);  in ipu_config_timing()
768 	conf = IPU_READ4(sc, DC_WRITE_CH_CONF_5);  in ipu_dc_enable()
788 	reg = IPU_READ4(sc, offset);  in ipu_dc_link_event()
802 	reg = IPU_READ4(sc, DC_MAP_CONF_VAL(ptr));  in ipu_dc_setup_map()
811 	reg = IPU_READ4(sc, DC_MAP_CONF_PTR(map));  in ipu_dc_setup_map()
826 	reg = IPU_READ4(sc, DC_MAP_CONF_VAL(map));  in ipu_dc_reset_map()
935 	reg = IPU_READ4(sc, DMFC_GENERAL_1);  in ipu_init_buffer()
950 	reg = IPU_READ4(sc, db_mode_sel);  in ipu_init_buffer()
969 		if (!(IPU_READ4(sc, IPU_MEM_RST) & IPU_MEM_RST_START))  in ipu_init()
1023 	reg = IPU_READ4(sc, IPU_CONF);  in ipu_init()
1033 	reg = IPU_READ4(sc, off);  in ipu_init()