Lines Matching +full:sync +full:- +full:on +full:- +full:green
1 /*-
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
63 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end)
64 #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay)
65 #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start)
66 #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end)
67 #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay)
68 #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start)
77 #define IPU_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
78 #define IPU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
79 #define IPU_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
80 device_get_nameunit(_sc->sc_dev), "ipu", MTX_DEF)
81 #define IPU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
83 #define IPU_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, (reg))
85 bus_write_4((_sc)->sc_mem_res, (reg), (value))
256 (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\
259 (_sc)->sc_mem_res, CPMEM_BASE + ch * (sizeof(*param)),\
412 mask = (1 << len) - 1; in ipu_ch_param_set_value()
413 data = param->word[word].data[datapos]; in ipu_ch_param_set_value()
416 param->word[word].data[datapos] = data; in ipu_ch_param_set_value()
419 len = bitpos + len - 32; in ipu_ch_param_set_value()
420 mask = (1UL << len) - 1; in ipu_ch_param_set_value()
421 data2 = param->word[word].data[datapos + 1]; in ipu_ch_param_set_value()
423 data2 |= (value >> (32 - bitpos)); in ipu_ch_param_set_value()
424 param->word[word].data[datapos + 1] = data2; in ipu_ch_param_set_value()
440 mask = (1UL << len) - 1; in ipu_ch_param_get_value()
441 data = param->word[word].data[datapos]; in ipu_ch_param_get_value()
445 len = bitpos + len - 32; in ipu_ch_param_get_value()
446 mask = (1UL << len) - 1; in ipu_ch_param_get_value()
447 data2 = param->word[word].data[datapos + 1]; in ipu_ch_param_get_value()
449 data |= (data2 << (32 - bitpos)); in ipu_ch_param_get_value()
458 …, 44, 45, 46, 68, 90, 94, 95, 113, 114, 117, 119, 120, 121, 122, 123, 124, 125, 138, 150, 151, -1}; in ipu_print_channel()
459 …0, 29, 58, 78, 85, 89, 90, 93, 95, 102, 116, 119, 122, 125, 128, 133, 138, 143, 148, 149, 150, -1}; in ipu_print_channel()
461 param->word[0].data[0], param->word[0].data[1], in ipu_print_channel()
462 param->word[0].data[2], param->word[0].data[3], in ipu_print_channel()
463 param->word[0].data[4]); in ipu_print_channel()
465 param->word[1].data[0], param->word[1].data[1], in ipu_print_channel()
466 param->word[1].data[2], param->word[1].data[3], in ipu_print_channel()
467 param->word[1].data[4]); in ipu_print_channel()
469 for (int i = 0; offset0[i + 1] != -1; i++) { in ipu_print_channel()
470 int len = offset0[i + 1] - offset0[i]; in ipu_print_channel()
472 offset0[i] + len - 1, in ipu_print_channel()
477 for (int i = 0; offset1[i + 1] != -1; i++) { in ipu_print_channel()
478 int len = offset1[i + 1] - offset1[i]; in ipu_print_channel()
480 offset1[i] + len - 1, in ipu_print_channel()
497 printf("GREEN: %d bits @%d\n", CH_PARAM_GET_GREEN_WIDTH(param) + 1, in ipu_print_channel()
525 + (wave_gen - 1) * sizeof(uint32_t); in ipu_config_wave_gen_0()
543 + (wave_gen - 1) * sizeof(uint32_t); in ipu_config_wave_gen_1()
554 + (wave_gen - 1) / 2 * sizeof(uint32_t); in ipu_config_wave_gen_1()
574 + (wave_gen - 1) * sizeof(uint32_t); in ipu_reset_wave_gen()
578 + (wave_gen - 1) * sizeof(uint32_t); in ipu_reset_wave_gen()
582 + (wave_gen - 1) / 2 * sizeof(uint32_t); in ipu_reset_wave_gen()
635 delta = abs(reference/i - freq); in ipu_calc_divisor()
658 freq = sc->sc_mode->dot_clock * 1000; in ipu_config_timing()
670 dw_gen = DW_GEN_DI_ACCESS_SIZE(div - 1) | DW_GEN_DI_COMPONENT_SIZE(div - 1); in ipu_config_timing()
681 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE); in ipu_config_timing()
687 sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK); in ipu_config_timing()
690 0, MODE_HSW(sc->sc_mode) * 2); in ipu_config_timing()
694 sc->sc_mode->vtotal - 1, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC), in ipu_config_timing()
699 0, MODE_VSW(sc->sc_mode) * 2); in ipu_config_timing()
702 IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1); in ipu_config_timing()
709 MODE_VSW(sc->sc_mode) + MODE_VFP(sc->sc_mode), DI_SYNC_COUNTER(DI_COUNTER_HSYNC)); in ipu_config_timing()
711 sc->sc_mode->vdisplay, DI_SYNC_COUNTER(DI_COUNTER_VSYNC), in ipu_config_timing()
715 0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK); in ipu_config_timing()
717 sc->sc_mode->hdisplay, DI_SYNC_COUNTER(DI_COUNTER_AD_0), in ipu_config_timing()
730 if (sc->sc_mode->flags & VID_NHSYNC) in ipu_config_timing()
735 if (sc->sc_mode->flags & VID_NVSYNC) in ipu_config_timing()
751 as_gen = SYNC_AS_GEN_VSYNC_SEL(DI_COUNTER_VSYNC - 1) | in ipu_config_timing()
757 IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay); in ipu_config_timing()
862 IPU_WRITE4(sc, DC_GEN, DC_GEN_SYNC_PRIORITY | DC_GEN_SYNC); /* High priority, sync */ in ipu_dc_init()
872 stride = sc->sc_mode->hdisplay * MODE_BPP / 8; in ipu_init_buffer()
877 CH_PARAM_SET_FW(¶m, sc->sc_mode->hdisplay - 1); in ipu_init_buffer()
878 CH_PARAM_SET_FH(¶m, sc->sc_mode->vdisplay - 1); in ipu_init_buffer()
879 CH_PARAM_SET_SLY(¶m, stride - 1); in ipu_init_buffer()
881 CH_PARAM_SET_EBA0(¶m, (sc->sc_fb_phys >> 3)); in ipu_init_buffer()
882 CH_PARAM_SET_EBA1(¶m, (sc->sc_fb_phys >> 3)); in ipu_init_buffer()
887 CH_PARAM_SET_NPB(¶m, 16 - 1); in ipu_init_buffer()
890 CH_PARAM_SET_RED_WIDTH(¶m, 5 - 1); in ipu_init_buffer()
892 CH_PARAM_SET_GREEN_WIDTH(¶m, 6 - 1); in ipu_init_buffer()
894 CH_PARAM_SET_BLUE_WIDTH(¶m, 5 - 1); in ipu_init_buffer()
896 CH_PARAM_SET_ALPHA_WIDTH(¶m, 8 - 1); in ipu_init_buffer()
968 while (i-- > 0) { in ipu_init()
976 device_printf(sc->sc_dev, "timeout while resetting memory\n"); in ipu_init()
985 dma_size = round_page(sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * (MODE_BPP / 8)); in ipu_init()
991 bus_get_dma_tag(sc->sc_dev), in ipu_init()
999 &sc->sc_dma_tag); in ipu_init()
1003 err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, in ipu_init()
1004 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_dma_map); in ipu_init()
1007 device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); in ipu_init()
1011 err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, in ipu_init()
1012 dma_size, ipu_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); in ipu_init()
1015 device_printf(sc->sc_dev, "cannot load DMA map\n"); in ipu_init()
1020 sc->sc_fb_size = sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * MODE_BPP / 8; in ipu_init()
1039 sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); in ipu_init()
1040 sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; in ipu_init()
1041 sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; in ipu_init()
1042 sc->sc_fb_info.fb_size = sc->sc_fb_size; in ipu_init()
1043 sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = MODE_BPP; in ipu_init()
1044 sc->sc_fb_info.fb_stride = sc->sc_mode->hdisplay * MODE_BPP / 8; in ipu_init()
1045 sc->sc_fb_info.fb_width = sc->sc_mode->hdisplay; in ipu_init()
1046 sc->sc_fb_info.fb_height = sc->sc_mode->vdisplay; in ipu_init()
1048 device_t fbd = device_add_child(sc->sc_dev, "fbd", in ipu_init()
1049 device_get_unit(sc->sc_dev)); in ipu_init()
1051 device_printf(sc->sc_dev, "Failed to add fbd child\n"); in ipu_init()
1055 device_printf(sc->sc_dev, "Failed to attach fbd device\n"); in ipu_init()
1068 if ((mode->dot_clock < 13500) || (mode->dot_clock > 216000)) in ipu_mode_is_valid()
1086 if (ei->edid_preferred_mode != NULL) { in ipu_pick_mode()
1087 if (ipu_mode_is_valid(ei->edid_preferred_mode)) in ipu_pick_mode()
1088 videomode = ei->edid_preferred_mode; in ipu_pick_mode()
1092 m = ei->edid_modes; in ipu_pick_mode()
1094 sort_modes(ei->edid_modes, in ipu_pick_mode()
1095 &ei->edid_preferred_mode, in ipu_pick_mode()
1096 ei->edid_nmodes); in ipu_pick_mode()
1097 for (n = 0; n < ei->edid_nmodes; n++) in ipu_pick_mode()
1121 device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); in ipu_hdmi_event()
1131 device_printf(sc->sc_dev, "failed to parse EDID\n"); in ipu_hdmi_event()
1138 device_printf(sc->sc_dev, "failed to find usable videomode\n"); in ipu_hdmi_event()
1142 sc->sc_mode = videomode; in ipu_hdmi_event()
1145 device_printf(sc->sc_dev, "detected videomode: %dx%d\n", in ipu_hdmi_event()
1146 videomode->hdisplay, videomode->vdisplay); in ipu_hdmi_event()
1150 CRTC_SET_VIDEOMODE(hdmi_dev, sc->sc_mode); in ipu_hdmi_event()
1163 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ipu")) in ipu_probe()
1180 sc->sc_dev = dev; in ipu_attach()
1182 sc->sc_mem_rid = 0; in ipu_attach()
1183 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, in ipu_attach()
1184 &sc->sc_mem_rid, RF_ACTIVE); in ipu_attach()
1185 if (!sc->sc_mem_res) { in ipu_attach()
1190 sc->sc_irq_rid = 0; in ipu_attach()
1191 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, in ipu_attach()
1192 &sc->sc_irq_rid, RF_ACTIVE); in ipu_attach()
1193 if (!sc->sc_irq_res) { in ipu_attach()
1195 sc->sc_mem_rid, sc->sc_mem_res); in ipu_attach()
1203 sc->sc_mem_rid, sc->sc_mem_res); in ipu_attach()
1205 sc->sc_irq_rid, sc->sc_irq_res); in ipu_attach()
1214 sc->sc_mem_rid, sc->sc_mem_res); in ipu_attach()
1216 sc->sc_irq_rid, sc->sc_irq_res); in ipu_attach()
1223 sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, in ipu_attach()
1245 return (&sc->sc_fb_info); in ipu_fb_getinfo()